The goal of the Graph-IC proof of concept proposal is to verify the innovation potential of silicon-technology-integrated graphene photodetectors for high-speed and broadband light conversion. The idea of this PoC is to use such graphene photodetectors as an enabling technology for integrated optoelectronic systems with extremely high data rates. The new technology will be fully integrated and allow the utilization of the entire transmission window of optical fibers. Such systems have the potential to decisively outperform existing systems in terms of data-rate, cost and energy consumption, which are becoming major challenges in large data systems. Within this PoC, we plan to establish the viability and identify technical issues of integrated graphene photodetectors with high electrical bandwidth for optical wavelengths. Graph-IC prepares the PI and his team to embark on a very high-risk, very high-gain endeavor, where the goal is to compete in a multi-billion Euro global market. This proposal is based on the scientific results of the ERC starting grant “InteGraDe – Integrating Graphene Devices (307311)”, where the PI has demonstrated the integration of graphene with silicon technology up to the wafer scale.

Two dimensional materials such as graphene and transition metal dichalcogenide (TMDC) are very sensitive to surface adsorbates and thus require proper encapsulation. In addition, functional devices based on those materials, like transistors, diodes or electro-optical modulators require high-k gate dielectrics to be deposited on top of the material. However, the deposition of high quality dielectric layers ontop of 2D materials is very challenging due to their inert surface. The project ECOMAT addresses the important challenge of depositing high-k dielectrics on top of 2D materials. In particular, the experienced researcher Dr. Barbara Canto will explore different routes to encapsulate graphene and MoS2, which is the most explored TMDC material, with different high-k dielectrics using a combination of atomic layer deposition and surface functionalization using seed layers. The key control parameters for those layers are dielectric constant, breakdown voltage, charge traps, minimal thickness achievable, and gas barrier properties, which will be characterized by electrical and spectroscopic methods. Finally a new route for fabricating low-resistive edge contacts to MoS2 will be explored, building up on encapsulated MoS2 layers. This contacting scheme is expected to significantly reduce contamination of the MoS2 layer during processing, while offering low-resistive contacts and thus will significantly increase the performance of electronic device based on MoS2. This interdisciplinary research activity builds up on the experience of Dr. Canto in the field of material science and physics and utilizes the infrastructure and knowledge at AMO on high-k dielectrics and electronic devices.

ENERGIZE aims to implement novel neuromorphic hardware based on two-dimensional (2D) materials for energy efficient artificial intelligence (AI). This technological breakthrough will be sustained on memristive, ferroelectric and floating gate two- and three-terminal devices based on 2D materials. ENERGIZE seeks to enhance the hardware for the implementation of artificial neural networks through chiplet-based multi-core in-memory computing technologies, providing also guidelines for evaluating and benchmarking 2D devices and circuits. ENERGIZE will be conducted by interconnected research integrating partners of Europe and Korea, accelerating the advancement of neuromorphic technology. ENERGIZE will demonstrate: wafer-scale growth of 2D materials for neuromorphic devices, reliable fabrication and characterization processes of two- and three-terminal devices, development of arrays of 2D devices compatible with existing technologies, efficient inference and training of neural networks in crossbar arrays and standardized benchmarking methods for neuromorphic devices and circuits. ENERGIZE offers a promising way to set a new paradigm in low-power edge computing, departing from conventional large energy consumption and high environmental impact von Neumann CMOS AI hardware. ENERGIZE aims to achieve substantial progress in the design, material growth, fabrication, integration, and characterization of neuromorphic devices, arrays, circuits, and systems, which will be key in the future of edge AI computing. We will contribute to guiding an ethically sensitive design by integrating social sciences and humanities by consulting. ENERGIZE will stimulate the emergence of a European – Korean collaborative network for responsible neuromorphic 2D material-based hardware. This integrated approach is a blueprint that will transform societies and economies of the future and will help Europe and Korea to enhance their position in chip technology for AI and machine learning applications.

G-IMAGER’s goal is to create added value through the introduction of high performing Graphene-on-wafer at competitive cost, accelerating innovation for the advanced electronic industry and eventually creating a new product category. This new area of development will make it possible for the European industry to harness this high market potential, fostering competitiveness and creating growth throughout the EU. The consortium proposes this project after an internal Business Innovation Plan, in order to take the CVD Graphene-on-wafer technology a step closer to the market through a new Graphene Imager product. This project will allow GS and EMB to become the worldwide leader as Graphene related electronics producers with the necessary production capacity to supply the industry and the research laboratories. More specifically, the G-IMAGER objectives are: • To develop ready-to-integrate Graphene-on-wafers for the advanced electronic industry. • To set up a customized rapid prototyping line and a new “foundry service”. • To produce a new Graphene Imager product and validate it for industrial acceptance. • Increase process yield and implement an automated and optimised quality control considering market requirements • Scale production capacity to more than 10,000 wafers/year to demonstrate commercial feasibility and business growth GS has validated and patented a highly efficient Graphene-on-wafer production process and its application into electronic devices. The consortium will be able to introduce Graphene Imager products at an industrial scale positively impacting the SWIR camera market of $ 1,100 M. The consortium will become the worldwide leader in Graphene-based advanced electronics and generate a cumulative net income of at least €60 M in four years and +33 jobs.

Challenging operating environments are common across many important internet of things (IoT) applications related to enterprises and the circular economy, including automotive, aerospace, industrial and power generation. However, conventional electronics are not suitable for operation in challenging and harsh environments, e.g. at high temperatures. i-EDGE establishes an enabling nanoelectromechanical (NEM) switch technology platform for IoT edge devices operating under demanding conditions, i.e., high temperature (<300 °C) and/or high-radiation (<1 Mrad), uses zero standby power, non-volatile memory and has low compute performance requirements. i-EDGE will realize a proof-of-concept demonstrator of a NEM “system-on-chip” (SoC) IoT node with an FPGA, non-volatile memory, and a temperature sensor, powered by a high-temperature capacitor bank, with a wireless power receiver for trickle charging the capacitor, and a simple data transceiver and sensor readout to interface to the on-chip FPGA and non-volatile memory. The FPGA fabric will be based on the NEM switch technology for digital logic, and integrated with a non-volatile memory array, analog utility blocks for wireless power transfer, data exchange and sensor readout. We will develop a NEM physical design kit (PDK) for design and circuit simulation, which will facilitate broad usage by application engineers. The technology and design flow will be demonstrated with a condition monitoring application, that has been developed for industrial IoT processes. In several previous EU and national projects, our technology has matured to TRL3 and i-EDGE will bring it to TRL5. The i-EDGE consortium has all expertise to establish a full supply chain, from basic logic and memory cell design to Systems-on-Chip and a migration path to pilot manufacturing of the NEM technology in Europe. Thus, i-EDGE will help position the EU at the cutting edge of chip design and manufacturing capabilities, as envisaged by the EU Chips Act.