This project proposes to design OpenCUBE, a full-stack solution of a validated European Cloud computing blueprint to be deployed on European hardware infrastructure. OpenCUBE will develop a custom cloud installation with the guarantee that an entirely European solution like SiPearl processors and Semidynamics RISC-V accelerators can be deployed reproducibly. OpenCUBE will be built on industry-standard open APIs using Open Source components and will provide a unified software stack that captures the different best practices and open source tooling on the operating system, middleware, and system management level. It will thus provide a solid basis for the European cloud services, research, and commercial deployments envisioned to be core for federated digital services via Gaia-X. To remain competitive for the European Green Deal, OpenCUBE is designed to make energy awareness a core feature at all levels of the stack, exploiting the advanced features of the SiPearl Rhea processor family at the hardware level and exposing the necessary API at the site level, up to and including interfaces to the electricity grid. This project will leverage representative workloads like those of ECMWF characteristics for production and Digital Twin workflows as drivers for the design and deployment of the cluster infrastructure. We will collaborate closely with the projects developing the virtual environments and the open hardware interfaces for current and future European processor and coprocessor technology.

Building on top of outcomes from the EPI and EUPilot projects, RISER will develop the first all-European RISC-V cloud server infrastructure, significantly enhancing Europe's open strategic autonomy. RISER will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including the RISC-V processor chips from EPI and EUPilot and LPDDR4 memories, in a novel energy-efficient cloud architecture. RISER brings together a set of 7 partners from industry and academia to jointly develop and validate open-source designs for standardized form-factor system platforms suitable for supporting cloud services. Specifically, RISER will build the following two cloud infrastructures: (1) An accelerator platform, which includes the ARM-based RHEA processor from EPI and a PCIe acceleration board that will be developed within the project which will integrate up-to four RISC-V based EPI and EUPilot chips. (2) A microserver platform, which interconnects up to ten microserver boards all developed by the project, each one supporting up to four RISC-V chips coupled with high-speed storage and networking. Embracing hyperconvergence, the microserver architecture will allow for distributed storage and memory to be used by any processor in the system with very low overhead. The open-source system board designs of RISER will also be accompanied by open-source low-level firmware and systems software, and a representative Linux-based software stack to support cloud services. To evaluate and demonstrate the capabilities of the RISER platforms we will develop three use cases: (a) Acceleration of compute workloads, (b) Networked object and key-value storage, and (c) Containerized execution as part of a provider-managed IaaS environment. RISER will offer open access to the microserver platform, facilitating uptake and enhancing the commercialization path of project results.

The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame. Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020: 1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features; 2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration); 3. develop key modules (IPs) needed for this implementation; 4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications; 5. explore the reuse of these building blocks to serve other markets than HPC. Our key choices are: a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance. b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor. c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.

Vitamin-V aims to develop a complete RISC-V open-source software stack for cloud services with iso-performance to the cloud-dominant x86 counterpart and a powerful virtual execution environment for software development, validation, verification, and test that considers the relevant RISC-V ISA extensions for cloud deployment. Specifically, commercial cloud systems make use of hardware features that are currently unavailable in RISC-V virtual environments (not to mention the lack of specific RISC-V hardware). These features include the virtualization, cryptography and vectorization for which Vitamin-V will add support in three virtual environments: QEMU, gem5 and cloud-FPGA prototype platforms. Vitamin-V focuses and will provide support for EPI-based RISC-V designs for both the main CPUs and cloud-important accelerators (for memory compression). We will add the compiler (LLVM-based) and toolchain support for the ISA extensions. Moreover, novel approaches for the validation, verification, and test of software trustworthiness will be developed considering. Vitamin-V will port and evaluate several cutting-edge VMMs and container suites (i.e. VOSySmonitor, KVM, QEMU, Docker, RustVMM, Kata containers), cloud management software (i.e., OpenStack, and Kubernetes) together with their software and libraries dependencies (e.g. JVM, Python); and AI (i.e Tensorflow) and BigData applications (Apache Spark). These software suites are representative of the three cloud setups that will be demonstrated: classical (OpenStack), modern (Kubernetes), and serverless (RustVMM, Kata, Kubernetes). The cloud setups will be benchmarked against relevant AI (i.e., Google Net, ResBet, VGG19), BigData (TPC-DS), and Serverless applications (FunctionBench, ServerlessBench). Vitamin-V aims to match the software performance of its x86 equivalent while contributing to RISC-V open-source virtual environments, software validation and cloud software suites.

HIGHER brings together 11 partners from industry and academia to jointly develop and validate open-source designs for high-density rack-scale systems capable of supporting cloud and edge services at scale in standards-based data center environments. Starting with the ARM RHEA2 and RISC-V EPAC processors from EPI and the RISC-V EUPilot processor chip, HIGHER adopts the Open Compute Project (OCP) Server family of standards to build processor modules for computation and acceleration, alongside a system security/control module, all operating with fully-featured operating systems and runtimes. HIGHER aims to design OCP server mechanics to provide modular rack systems incorporating reusable standards-based infrastructure, encompassing hardware, low-level firmware, and systems software, ensuring trustworthy functionality for managing, securing, and controlling servers. The project's open-source hardware and software outcomes will enhance European Digital Autonomy and facilitate wide adoption. Furthermore, the project will assemble representative software stacks supporting a range of use cases, including accelerated data processing and analysis for converged Cloud and HPC platforms, Infrastructure-as-a-Service with standardized management and monitoring, Platform-as-a-Service facilitating large-scale data processing for ML inference and data analytics, and memory pool management at the server rack level, with access control safeguards aligned with maturing CXL standards.