Data centers which underpin the Cloud are under pressure. As the capacity of data center servers is growing, so must the capacity of the links between those servers. Industry foresees a need for high volumes of 800Gb/s and 1.6Tb/s transceivers by 2025. Today, despite the use of complex Photonic Integrated Circuits (PICs), manufacturing an optical transceiver still requires a large number of sequential steps. This is because lasers and electronic chips need to be assembled on a piece-by-piece basis onto the PIC. The resulting optical engine then needs to be coupled to a fiber array and packaged. These steps are done sequentially, creating a bottleneck in the manufacturing line which makes it hard to scale up production and reduce cost. CALADAN will demonstrate how integration of lasers and electronics onto a PIC can be done fully at the wafer-level using the established micro transfer printing technique, thus eliminating this bottleneck. GaAs quantum dot lasers and 130nm SiGe BiCMOS 56Gbaud capable driver and receiver electronics will be transfer printed onto Silicon Photonic 300mm wafers. Starting from proven concepts in PIXAPP, a novel fast fiber attachment process will be demonstrated that reduces the time required for fiber attachment by an order of magnitude. Using these techniques, transceiver cost will be 0.1Euro/Gb/s for volumes of at least 1,000,000 units. The consortium, which consists of three SMEs (X-Celeprint, Innolume and ficonTEC), an LE (EVGroup), three research institutes (IMEC, Tyndall and IHP), a transceiver manufacturer (Mellanox) and a multinational (Xilinx) encompasses all the partners to start production of the targeted optical transceivers after the end of the project. Exploitation of the technology will be supported by an end-user (British Telecom), a semiconductor foundry setting up a micro transfer printing Pilot Line (MICROPRINCE, X-FAB), an optical equipment manufacturer (ADVA) and the European Photonic Industry Consortium (EPIC).

Artificial neural networks have been shown to offer a powerful computing approach to encounter many classification problems as in synthetic vision (e.g. autonomous driving) and artificial intelligence (e.g. AlphaGo). While their implementations are often based on power-hungy CPU- and GPU-installations, first researchers have delivered initial application-specific solutions that demonstrate FPGAs to be a feasible and efficient alternative. This proposal aims at providing a generic reference implementation of ANNs on FPGAs that is tunable towards various application needs by parametrization. Since individual FPGA designs establish enormous costs of entry due to a higher engineering effort on a lower abstration level, an IP core that is available out of the box is a great R&D incentive that enables more researchers and engineers to embrace the emerging efficient heterogeneous computing more quickly and produce innovations and more compact and more efficient products on this basis. Besides this technological advance, this proposal enables a researcher with an enormous experience in mapping computations into FPGA hardware to make a valuable industrial experience in an international context with the major company in this domain. His expertise is ideally complemented with the application experience available at Xilinx who will benefit from opening a new growing market for manufactured FPGA devices. The development of the researcher's skill set is explictly addressed by complementing his academic background with industrial experience and scheduled cooperate trainings. As part of the dissemination activities, his network into the FPGA community is strengthened and approaches towards the ANN community are made.

Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of systems on chip (SoC), e.g. NVIDIA Jetson, Xilinx UltraScale+ FPGA, ARM big.LITTLE. However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a significant increase in numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g. due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults. In complex living organisms, the nervous system is a much more efficient and adaptive "subsystem" that detects environmental changes and anomalies that impact them by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. Nervous systems naturally scale up, adapt and operate autonomously in a de-centralised manner. In NERVOUS our vision is to rejuvenate modern electronic systems and particularly the way in which such systems are designed to act autonomously to become more reliable. The goal of NERVOUS is to develop a methodology for "self-aware" electronic systems with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous tolerance of faults. NERVOUS is an inter-disciplinary collaboration that brings together networks of spiking neurons with electronic systems, so that they form hardware platforms with inherently embedded artificial "nervous systems". This approach has never before been used to make the technology we all carry around in our pockets more efficient and reliable, making NERVOUS "blue-skies" research at the cutting edge of bio-inspired electronic systems design. To ensure feasibility, NERVOUS's research programme is built around a number of hardware demonstrators of increasing complexity. NERVOUS is making use of state-of-the-art UltraScale+ FPGAs for rapid prototyping of nervous system components and complementing with an electronic design environment. To ensure accessibility beyond the project, NERVOUS will develop a design methodology and an EDA tool supporting automatic integration and training of NERVOUS components with traditional circuit designs, allowing engineers to apply our technology without having to worry about the intricate details of electronic-neuron interfacing. NERVOUS will demonstrate this for digital FPGA designs at the HDL level in collaboration with Xilinx. To ensure scalability, we will verify and evaluate the NERVOUS methodology on a range of relevant large-scale processor designs provided by our partner ARM, who will also advise on fault performance requirements. To ensure a route to industrial application and exploitation, we will demonstrate the NERVOUS methodology in the context of a real-word space application, e.g. space networking IP and modular spacecraft controller, through collaboration and secondments with our project partner TAS-UK.

The performance of programming language implementations until 10 years ago relied on increasing clock frequencies on uni-core CPUs. The last decade has seen the rise of the multi-core era adding processing elements to CPUs, to enable general purpose parallel computing. Due to a single connection from multiple cores on a CPU to main memory, general purpose languages with parallelism support are finding the limits of general purpose CPU architectures that have been extended with parallelism. The fabric on which we compute has changed fundamentally. Driven by the needs of AI, Big Data and energy efficiency, industry is moving away from general purpose CPUs to efficient special purpose hardware e.g. Google's Tensorflow Processing Unit (TPU) in 2016, Huawei's Neural Processing Unit (NPU) in smartphones, and Graphcore's Intelligent Processing Unit (IPU) in 2017. This reflects a wider shift to special purpose hardware to improve execution efficiency. Functional languages are gaining widespread use in industry due to reduced development time, better maintainability, code correctness with assistance of static type checkers, and ease of deterministic parallelism. Functional language implementations overwhelmingly target general purpose CPUs, and hence have limited control over cache behaviour, sharing, prefetching and garbage collection locality. As such, they are reaching their performance limits due to the trade-off between parallelism and memory contention. This project takes the view that rather than using compiler optimisations to squeeze small incremental performance improvements from CPUs, special purpose hardware on programmable FPGAs may instead be able to provide a step change improvement by moving these non-deterministic inefficiencies into hardware. Graph reduction is a functional execution model that offers intriguing opportunities for developing radically different processor architectures. Early ideas stem back to the 1980s, well before the age of advanced Field Programmable Gate Array (FPGA) technology of the last 5-10 years. We believe that a bespoke FPGA memory hierarchy for functional languages could minimise memory traffic, thus avoiding the costs of cache misses and memory access latencies that quickly become the bottleneck for medium and large sized functional programs. We believe that lowering key runtime system components (prefetching, garbage collection, parallelism) to hardware, with a domain specific instruction set for graph reduction, will significantly reduce runtimes. We aim to inspire the computer architecture community to extend this project by developing accurate cost models for functional languages that target special purpose functional language hardware. Our HAFLANG project will target the Xilinx Alveo U280 accelerator board, a state-of-the-art UltraScale+ FPGA-based platform as a research vehicle for developing the FPU. The HAFLANG compilation framework will be designed to be extensible, and hence make the FPU processor a target for other languages in future. By developing a hardware accelerator, we believe it is possible to engineer a processor that (1) will execute programs with twice the throughput compared with GHC compiled Haskell executing on conventional mid-tier 4-16 core x86/x86-64 CPUs, and (2) consumes four times less energy than by executing programming languages on CPUs.

Electech, covering areas such as sensors, power electronics, embedded computing, wireless communication technology, autonomous systems and large-area electronics, is predicted to play a foundational role in the future development of industries and value chains. It is central to Innovate UK's core strategy and its importance to future economic growth cannot be overstated. It is vital that the UK maintains a strong electronics design and technology base in the face of international developments. The proposed European chips act (February 2022), will mobilise 43 43 billion euros by 2030 in 'policy-driven investment' for the EU's semiconductor sector. The US CHIPS Act will result in a $280 billion investment to bolster their semiconductor capacity, catalyse R&D, create regional high-tech hubs and grow a more inclusive STEM workforce. The UK has a very vibrant but dispersed, electronic systems academic community, organised into larger activities in the universities of Glasgow, Imperial College London, Liverpool, Manchester, Newcastle, Sheffield, Southampton, University College London and Queen's University Belfast as well as satellite activities in a range of other universities. The community have been able to organise into an effective electronic systems community via the eFutures network (EPSRC eFutures2.0: Addressing Future Challenges grant, May2019-2023). In addition to growing the community, the objectives of the existing eFutures2.0 network had been to explore multidisciplinary opportunities for the sector. The successes of eFutures include: the organisation of 20+ in-person and online events (1825 attendees); the creation of a new website and a YouTube channel with 34 videoed talks (speakers from 19 countries) with a total of 1180 views; increased network membership by over 400% and move from a pure mailout model to include social media, achieving 64% of event attendees who had not previously engaged with the network; the delivery of two new, strategic landscaping reports: 'UK Landscape in AI & Brain-Inspired Computing Hardware' (Q4 2021) and 'Electronics for Healthcare: R&D across the UK' (expected Q1 2023). The 2021 Report had national media coverage, follow-up events (150 attendees), an upcoming, high-value proposal and a mention in the EPSRC Delivery Plan. The Healthcare Report results from online and in-person events (264 attendees) leading to a Programme Grant proposal. The network funded six multidisciplinary, concept projects (£78k), benefitting 11 academics across ten UK and four international universities; and delivered focussed engagement with 59 early-career and 30 mid-career researchers via two in-person workshops and online training. Ultimately, the aim is to further enhance the impact of UK electronics systems academic research and put the community in a strong, competitive position for collaboration with both national and international researchers, and industry. As highlighted above this will be achieved by continuing to build and growing network membership, organising the Net-Zero multidisciplinary event to engage our community more broadly in the area with other academic areas and companies to tackle this key topic, represent a strong focus on the electronics systems academic community in the UK, supporting early career researchers and growing the community by encouraging interaction or the national and international level and increasing the funding. We will achieve this by building on the successes of the eFutures2.0 activity with the same leadership team and steering group. The success and commitment to this activity is indicated by the in-kind commitment of £64,000 from our steering group companies.