Aquaculture is an important source for food, nutrition, income and livelihoods for millions of people around the globe. Intensive fish farming is often associated with pathogen outbreaks and therefore high amounts of veterinary drugs are used worldwide. As in many other environments, mostly application of antimicrobials triggers the development of (multi)resistant microbiota. This process might be fostered by co-selection as a consequence of the additional use of antiparasitics. Usage of antimicrobials in aquaculture does not only affect the cultured fish species, but - to a so far unknown extent - also aquatic ecosystems connected to fish farms including microbiota from water and sediment as well as its eukaryotes. Effects include increases in the number of (multi)resistant microbes, as well as complete shifts in microbial community structure and function. This dysbiosis might have pronounced consequences for the functioning of aquatic ecosystems. Thus in the frame of this project we want to study consequences of antimicrobial/-parastic application in aquaculture for the cultured fish species as well as for the aquatic environments. To consider the variability of aquaculture practices worldwide four showcases representing typical systems from the tropics, the Mediterranean and the temperate zone will be studied including freshwater and marine environments. For one showcase a targeted mitigation approach to reduce the impact on aquatic ecosystems will be tested.

In a world where electrical energy plays a more and more important role in the energy mix in reason of the worldwide increasing use of renewable energies, the market of Power Electronic Conversion Systems (PECS) is constantly growing in size and in complexity to address the need and challenges of electric power conversion at all levels. Today’s PECS market is largely dominated by silicon-based technology, as it is low-cost and mature. However, this technology limits the trade-off between size, energetic efficiency and maximum operating voltage due to the intrinsic limitation of the Si semiconductor. While emerging technologies such as electric vehicles and further applications keep demanding higher performance for operating voltage up to the kV range, it appears crucial to overcome these limitations to follow these major technological changes. One promising solution to this problem is the use of wide-bandgap semiconductor technologies Gallium Nitride (GaN) which is far superior in terms of electron mobility and breakdown voltage. GaN technology is presently being used in applications up to 650V by means of horizontally-configured high electron mobility transistors (HEMTs) on foreign substrates (Si or SiC). Although GaN HEMT technology is exhibiting impressive performance, we are still not using all the capabilities of this material owing to several limitations caused by the growing of GaN epi-layer in on foreign substrate. On the other hand, recent progress in material science have enabled the fabrication of GaN substrates at reasonable costs. Therefore, in this project, we target to overcome these limitations by using a GaN substrate and a homo-epitaxial growth approach to fabricate Vertical GaN transistors (MOSVFETs). Indeed, previous works in literature have demonstrated the tremendous gain of power density with the vertical approach on GaN bulk substrate. The cutting-edge idea driving this proposal is the monolithic combination of horizontal HEMT and vertical MOSVFET transistors within the same chip. What makes this proposal stand out from previous works is the fact that, for the first time, we will demonstrate the monolithic integration of a high-speed HEMT-based driver with a high-voltage MOSVFET-based power switch. This approach enables to benefit from the superiority of normally-off GaN MOSVFETs in terms of specific ON-resistance while enabling the integration of a driver circuit featuring GaN HEMTs for very high speed switching. The result will be a state-of-the-art PECS capable of handling voltage up to 1200V with exceptional characteristics in terms of robustness, reactivity, power density and efficiency, all thanks to the combination of both configuration: high-voltage handling and current density of vertical devices and high cut-off frequency of horizontal devices. This technological challenge represents thus a significant breakthrough while being achievable by current expertise and technological capabilities of the partners of this project.

GaN devices offer attractive alternatives to existing silicon technologies to meet the growing demand for high-power electronic devices. GaN's wide bandgap enhances device breakdown voltage and reduces on-state resistance compared to traditional silicon in unipolar devices. However, the performance limitations of these conventional devices can be overcome by using Super-Junction (SJ) technology, demonstrated experimentally in both Si and SiC technologies. Due to current challenges related to buried selective doping in GaN material, fabricating vertical GaN SJ devices remains a significant challenge, with no published experimental results to date. To address these limitations, we propose an innovative technology implementing lateral PN junctions in GaN Nanowires to create the next generation of vertical GaN SJ devices. These new devices will exhibit a breakdown voltage and on-state resistance of 650V and 0.02O cm², respectively, for a 2 mm thick drift region. The consortium comprises four public research laboratories: LN2 (Laboratoire Nanotechnologies Nanosystèmes), C2N (Centre des nanosciences et nanotechnologie), LTM (Laboratoire des Technologies de la Microélectronique), and Ampere, covering a wide range of expertise and applied knowledge. The partners' complementary expertise in GaN activities is a key factor contributing to the project's success. For these academic laboratories, participating in the Super-GaN project represents an excellent opportunity to develop new expertise, generate significant scientific impact, and create economic value.

The electrification of means of transport requires the development of converters from battery DC voltage to AC voltage for vehicule motorisations. An increase in the performance of these power converters requires power electronic components with very good performance as Gallium Arsenide (GaN) transistors. The consequence is a very high-power density to be dissipated in heat (> 500 W/cm2). The aim of this project is to propose an innovative thermal management of this type of converter by producing in a single piece the device for removing the heat from the transistors to the surrounding environment. An enclosure allowing direct thermal contact between the transistor housings and a liquid, ideally water, forms the evaporator of a heat pipe. The condenser, in the form of hollow fins, completes this unique part made of technical polymer with a thin copper deposit, all produced by plastronic techniques. The heatsink designed in this way eliminates the contact resistances that are prevalent in a conventional assembly. The project is divided into six lots. Lot 1, which is based on previous work between the partners, aims to design, develop and characterize plastronic heat pipes by assembling 3D printed parts using stereolithography. The visualization of the physical phenomena operating within the heat pipe - boiling on the heated surface and condensation in the hollow fins - will allow a better understanding of its operating limits and the implementation of effective methods to push them. Lot 2 explores the possibilities of manufacturing and operating a heat pipe using an industrializable process, requiring the use of a thermoplastic polymer such as polycarbonate. Although, at this stage, the parts will be made by thermoforming and extrusion processes, the shapes chosen will be compatible with an injection moulding process. The demonstration of a solution for dismantling the plastronic device is planned. Lot 3 will look for the optimal thermoplastic polymer with regard to the criteria for choosing the heat pipe, manufacturing constraints and recyclability. In lot 4, three electronic test vehicles will be designed first by conventional manufacturing with classical PCB, then by plastronics. Three developments will be considered: densification of the positioning of the GaN transistors in relation to each other, increase in the chopping frequency, design of a high-power converter (30 kW). Lot 5, dedicated to the manufacture of heat pipes, will supply the other lots. Finally, lot 6 will focus on the Life Cycle Assessment of the alternative device to evaluate the environmental impacts, linked for example to the reduction of mass, and linked to technological indicators such as recyclability. The CaPReP project, coordinated by the Energetic and Thermal center of Lyon (CETHIL), brings together the Power Electronics and Plastronics teams of the AMPERE laboratory, as well as the Institute of Polymer Materials (IMP). The electronic/thermal co-design methodology developed is of great interest, particularly for exploring different ways of improving electronics. Thanks to the collaboration of recognized partners, this multidisciplinary project with a high potential for innovation will enable the "plastronic heat pipe" technology to move from TRL3 to TRL4, thus meeting strong scientific, technological and environmental challenges. The results of the project will be likely to generate contracts with the plastics or electronics industries.

The deployment of renewable energy involves a mutation of the electric grids to account these new sources. Particularly, HVDC and MVDC grids are new technologies that demand high voltage power electronic converters. Silicon carbide (SiC) is a good material for high-voltage power devices while Gallium Nitride (GaN) is limited in voltage range and diamond remains a long-term target. 10 kV and above SiC-devices are targeted in research projects while 3.3 kV devices are under industrialization. However, to achieve high voltage power converters, it is needed to associate in series power modules or power components. So, one main issue is the design of highly insulated drivers (up to several 100 kV). There exists some solutions as the self-supplying but these solutions are complex and may decrease the global reliability of the system. On the other hand, the photo-transistor is a classic device, and it is very common for the silicon ones. If some optical controlled SiC thyristors have been demonstrated, to our knowledge an optical controlled SiC Bipolar Junction Transistors (BJT) has not yet been demonstrated for high voltage applications. The advantage of the photo-transistor is to avoid the use of a circuit driver because of the electrical insulation may be easily achieved by an optical fiber. So, the project proposes the design and fabrication of a high-voltage phototransistor. The interest of such a power device is very high because of the simplification of the drive insulation. Moreover, for a given die area, the BJT is the best component with the lower on-loss among all other SiC power semiconductor devices. The consortium consists of 2 academic partners (Ampere Lab. and ISL) and one SME (NovaSiC). NovasiC will optimize a fast chemical vapor deposition (CVD) for the low-doping thick epitaxial layer (n-type) needed to reach 10 kV devices. The target is to reduce the cost of this process which is a significant part of the global process costs for such high-voltage devices. The obtained results will be compared to commercial epitaxial-layers. The project proposes the fabrication and the test of high voltage photo-transistors, BJTs, on two batches of fabrications. To reduce the risks in the project, some transistors on the wafers will have a base metalization to enable electrical tests. This type of cells may be used for the 4 targeted devices of the project. All of them are high voltage vertical devices with the target of 10 kV. This blocked voltage target has the advantage to be interesting for numerous applications (e-transformer, modules for HVDC or MVDC applications, DC breakers …) and not to be so difficult to be fabricated in an academic clean-room. However for a efficient BJT, the requirement for accurate process is high in terms of photolithography, dry etching, passivation and packaging. So technological facilities of the ESIEE are targeted which is recognized for its professionalism and support of research projects developed on its 600 m2 clean-room, offering a full 100 to 150 mm technology which is ideal for the actual SiC wafer sizes (4 to 6 inches). To avoid strong constraints on the device fabrication, a solution is to develop all the high voltage BJTs on the same wafer (2 lots). Depending on the project results, some targeted products are expected • Large 10 kV photo-transistors for efficient and isolated converters (HVDC, MVDC), DC Breaker (solid state). • Large 10 kV Photo-Darlington for all applications where the efficiency is not critical : single pulse applications, DC breakers (hybrid), active snubber ... • 10 kV optical switch 10 kV, i.e. a large BJT with a low voltage silicon phototransisor and a self-supply : a bypass of the first target to compare phototransisor to more classical solution. • Large 10 kV (even 15 kV) or 3.3 kV BJTs, as an alternative of SiC-MOSFETs without the gate oxide reliability issues for applications where a high efficiency is required: HVDC, MVDC, electric traction…