MULTI-MOBY is an ambitious proposal aiming at quickly finalizing the results of a cluster of GV and FoF EU projects addressing the development of technology for safe, efficient and affordable urban electric vehicles. A fleet of multi-passenger and multi-purpose commercial vans will be manufactured assuring: • Best-in-class safety for occupants and Vulnerable Road Users (VRUs) protection as required per the M1/N1categories, • Autonomous capabilities by adopting the most on-the-road-experimented sensing and computational platforms, with the addition of low-cost scanning and night vision functionalities, • High efficiency 48V and 100V powertrains adopting the most advanced power semiconductor technologies amongst Si, SiC and GaN, • Robust battery packs based on hybrid cells with specific energy close to 200Wh/kg at pack level, • On-board charger integrating a DCxxV-DC12V converter optimized for the two voltages of interest, • A standardized low cost charging system able to operate DC charging at 48V and 100V, • Advanced Electric Electronic (EE) architecture with implemented secured procedures for remote updates and upgrades of the firmware and predictive maintenance, by applying advanced artificial intelligence (AI) methodologies, • Application of low-cost, flexible, agile and lean manufacturing through a low-investment micro-factory concept, • Competitive price positioning with respect to existing and forthcoming fully electrical urban passenger and commercial vehicles.

In line with industry needs, Moore’s law, scaling in ITRS 2013/2015, and ECSEL JU MASP 2016, the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5 nm node. This is planned with available EUV/NA0.33 scanners that are optimized for mix and match with existing DUV/NA1.35 scanners, and with system design and development of a new hyper NA EUV lithography tool to enable more single exposure patterning at 5 nm to create complex integrated circuits. Process steps for modules in Front-end, Middle and Back-end of line are discovered and developed using the most advanced tool capabilities and they are evaluated morphologically and electrically using a relaxed test vehicle. During the development, specific challenges in metrology are assessed and metrology tools are upgraded or newly developed. The results are demonstrated in the imec pilot line with qualified metrology tools at the 5 nm node. The TAKEMI5 project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets, as set out in the MASP, at a (disruptive) new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the module integration of electronic devices for the 5nm node in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law which has celebrated its 50th anniversary. The cost aware development process supports the involved companies, and places them in an enhanced position for their worldwide competition. Through their worldwide affiliations, the impact of the TAKEMI5 project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.

The objective of the ACT10 project is to develop and demonstrate the required technology options, including their integration, for the 10Ångstrom node. The 32 participating partners cover a wide range of activities along the entire value chain for the manufacturing of CMOS chips. Activities include equipment development, computer aided design tooling and process technology development. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The project aims to enhance the attractiveness of the EU as a location for new cutting-edge high volume and legacy node fabs. The ACT10 project is built based on the following four pillars. 1. Lithography Equipment and Mask Technology: Increase key-performance indicators in the optical system of High-NA Lithography machines, along with developing advanced mask processes and equipment to reach optical imaging requirements, and nonlinear optics material lifetime effects. 2. Chip design and Block Level validation; Assessment of different CFET devices and evaluate building blocks for digital and analog IPs. 3. Process Technology: development of innovative solutions for routing of the stacked n- and p-devices of the CFET architecture, development of 0.55NA (high-NA) single patterning solutions, and the development of semi-damascene BEOL for the 10Å node. 4. Computational Metrology and Process Monitoring Equipment: develop computational metrology methods, and develop metrology and inspection modules and equipment.

The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7’s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies – More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.

The metrology domain (which could be considered as the ‘eyes and ears’ for both R&D&I and production) is a key enabler for productivity enhancements in many industries across the electronic components and system (ECS) value chain and have to be an integral part of any Cyber Physical Systems (CPS) which consist of metrology equipment, virtual metrology or Industrial internet of things (IIoT) sensors, edge and high-performance computing (HPC). The requirements from the metrology is to support ALL process steps toward the final product. However, for any given ECS technology, there is a significant trade-off between the metrology sensitivity, precision and accuracy to its productivity. MADEin4 address this deficiency by focusing on two productivity boosters which are independent from the sensitivity, precision and accuracy requirements: • Productivity booster 1: High throughput, next generation metrology and inspection tools development for the nanoelectronics industry (all nodes down to 5nm). This booster will be developed by the metrology equipment’s manufacturers and demonstrated in an industry 4.0 pilot line at imec and address the ECS equipment, materials and manufacturing major challenges (MASP Chapter 15, major challenges 1 – 3). • Productivity booster 2: CPS development which combines Machine Learning (ML) of design (EDA) and metrology data for predictive diagnostics of the process and tools performances predictive diagnostics of the process and tools performances (predictive yield and tools performance). This booster will be developed and demonstrated in an industry 4.0 pilot line at imec, for the 5nm node, by the EDA, computing and metrology partners (MASP Chapter 15, major challenge 4). The same CPS concept will be demonstrated for the ‘digital industries’ two major challenges of the nanoelectronics (all nodes down to 5nm) and automotive end user’s partners (MASP Chapter 9, major challenges 1and 3).