publication . Preprint . 2020

The gem5 Simulator: Version 20.0+

Lowe-Power, Jason; Ahmad, Abdul Mutaal; Akram, Ayaz; Alian, Mohammad; Amslinger, Rico; Andreozzi, Matteo; Armejach, Adrià; Asmussen, Nils; Beckmann, Brad; Bharadwaj, Srikant; ...
Open Access English
  • Published: 06 Jul 2020
Abstract
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to model modern computer hardware at the cycle level, and it has enough fidelity to boot unmodified Linux-based operating systems and run full applications for multiple architectures including x86, Arm, and RISC-V. The gem5 simulator has been under active development over the last nine years since the original gem5 release. In this time, there have been over 7500 commits to the codebase from over 250 unique contributors which have improved the simulator by adding new features, fixing bugs, a...
Subjects
free text keywords: Computer Science - Hardware Architecture
Funded by
EC| Mont-Blanc 2020
Project
Mont-Blanc 2020
Mont-Blanc 2020, European scalable, modular and power efficient HPC processor
  • Funder: European Commission (EC)
  • Project Code: 779877
  • Funding stream: H2020 | RIA
,
NSF| CRII: CSR: Programmable Heterogeneous Memory Systems via Multiple Address Spaces and RAM Lake
Project
  • Funder: National Science Foundation (NSF)
  • Project Code: 1850566
  • Funding stream: Directorate for Computer & Information Science & Engineering | Division of Computer and Network Systems
Download from
74 references, page 1 of 5

[1] 2012. IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666-2011 (Revision of IEEE Std 1666-2005) (Jan 2012). https://doi.org/10.1109/ IEEESTD.2012.6134619

[2] 2020. pybind11. https://pypi.org/project/pybind11/.

[3] Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, and Niraj K Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 33-42.

[4] Ayaz Akram and Lina Sawalha. 2016. x86 Computer Architecture Simulators: A Comparative Study. In IEEE 34th International Conference on Computer Design (ICCD). IEEE, 638-645.

[5] Ayaz Akram and Lina Sawalha. 2019. Validation of the gem5 Simulator for x86 Architectures. In 2019 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS). IEEE, 53-58.

[6] Alaa R Alameldeen and Rajat Agarwal. 2018. Opportunistic compression for direct-mapped DRAM caches. In Proceedings of the International Symposium on Memory Systems. ACM, 129-136.

[7] Fawaz Alazemi, Arash AziziMazreah, Bella Bose, and Lizhong Chen. 2018. Routerless Network-on-Chip. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018. IEEE Computer Society, 492-503. https://doi.org/10.1109/HPCA.2018.00049 [OpenAIRE]

[8] M. Alian, U. Darbaz, G. Dozsa, S. Diestelhorst, D. Kim, and N. S. Kim. 2017. dist-gem5: Distributed Simulation of Computer Clusters. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 153-162. https://doi.org/10.1109/ISPASS.2017.7975287 [OpenAIRE]

[9] M. Alian, D. Kim, and N. Sung Kim. 2016. pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems. IEEE Computer Architecture Letters 01 (jan 2016), 41-44. https://doi.org/10.1109/LCA.2015.2438295 [OpenAIRE]

[10] Tiago Alves and Don Felton. 2004. TrustZone: Integrated Hardware and Software Security. Information Quarterly (2004), 18-24.

[11] AMD. 2012. AMD Graphics Core Next (GCN) Architecture. https://www. techpowerup.com/gpu-specs/docs/amd-gcn1-architecture.pdf.

[12] AMD. 2016. Graphics Core Next Architecture, Generation 3. http: //developer.amd.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_ Architecture_rev1.1.pdf.

[13] Arm Ltd. 2020. ArmÂő Architecture Reference Manual: Armv8, for Armv8-A architecture profile (f.b ed.). Arm Ltd. https://developer.arm.com/docs/ddi0487/fb/ arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

[14] Mochamad Asri, Ardavan Pedram, Lizy K John, and Andreas Gerstlauer. 2016. Simulator Calibration for Accelerator-Rich Architecture Studies. In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS),. IEEE, 88-95.

[15] David H Bailey, Eric Barszcz, John T Barton, David S Browning, Robert L Carter, Leonardo Dagum, Rod A Fatoohi, Paul O Frederickson, Thomas A Lasinski, Rob S Schreiber, et al. 1991. The NAS parallel benchmarks. The International Journal of Supercomputing Applications 5, 3 (1991), 63-73.

74 references, page 1 of 5
Abstract
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to model modern computer hardware at the cycle level, and it has enough fidelity to boot unmodified Linux-based operating systems and run full applications for multiple architectures including x86, Arm, and RISC-V. The gem5 simulator has been under active development over the last nine years since the original gem5 release. In this time, there have been over 7500 commits to the codebase from over 250 unique contributors which have improved the simulator by adding new features, fixing bugs, a...
Subjects
free text keywords: Computer Science - Hardware Architecture
Funded by
EC| Mont-Blanc 2020
Project
Mont-Blanc 2020
Mont-Blanc 2020, European scalable, modular and power efficient HPC processor
  • Funder: European Commission (EC)
  • Project Code: 779877
  • Funding stream: H2020 | RIA
,
NSF| CRII: CSR: Programmable Heterogeneous Memory Systems via Multiple Address Spaces and RAM Lake
Project
  • Funder: National Science Foundation (NSF)
  • Project Code: 1850566
  • Funding stream: Directorate for Computer & Information Science & Engineering | Division of Computer and Network Systems
Download from
74 references, page 1 of 5

[1] 2012. IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666-2011 (Revision of IEEE Std 1666-2005) (Jan 2012). https://doi.org/10.1109/ IEEESTD.2012.6134619

[2] 2020. pybind11. https://pypi.org/project/pybind11/.

[3] Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, and Niraj K Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 33-42.

[4] Ayaz Akram and Lina Sawalha. 2016. x86 Computer Architecture Simulators: A Comparative Study. In IEEE 34th International Conference on Computer Design (ICCD). IEEE, 638-645.

[5] Ayaz Akram and Lina Sawalha. 2019. Validation of the gem5 Simulator for x86 Architectures. In 2019 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS). IEEE, 53-58.

[6] Alaa R Alameldeen and Rajat Agarwal. 2018. Opportunistic compression for direct-mapped DRAM caches. In Proceedings of the International Symposium on Memory Systems. ACM, 129-136.

[7] Fawaz Alazemi, Arash AziziMazreah, Bella Bose, and Lizhong Chen. 2018. Routerless Network-on-Chip. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018. IEEE Computer Society, 492-503. https://doi.org/10.1109/HPCA.2018.00049 [OpenAIRE]

[8] M. Alian, U. Darbaz, G. Dozsa, S. Diestelhorst, D. Kim, and N. S. Kim. 2017. dist-gem5: Distributed Simulation of Computer Clusters. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 153-162. https://doi.org/10.1109/ISPASS.2017.7975287 [OpenAIRE]

[9] M. Alian, D. Kim, and N. Sung Kim. 2016. pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems. IEEE Computer Architecture Letters 01 (jan 2016), 41-44. https://doi.org/10.1109/LCA.2015.2438295 [OpenAIRE]

[10] Tiago Alves and Don Felton. 2004. TrustZone: Integrated Hardware and Software Security. Information Quarterly (2004), 18-24.

[11] AMD. 2012. AMD Graphics Core Next (GCN) Architecture. https://www. techpowerup.com/gpu-specs/docs/amd-gcn1-architecture.pdf.

[12] AMD. 2016. Graphics Core Next Architecture, Generation 3. http: //developer.amd.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_ Architecture_rev1.1.pdf.

[13] Arm Ltd. 2020. ArmÂő Architecture Reference Manual: Armv8, for Armv8-A architecture profile (f.b ed.). Arm Ltd. https://developer.arm.com/docs/ddi0487/fb/ arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

[14] Mochamad Asri, Ardavan Pedram, Lizy K John, and Andreas Gerstlauer. 2016. Simulator Calibration for Accelerator-Rich Architecture Studies. In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS),. IEEE, 88-95.

[15] David H Bailey, Eric Barszcz, John T Barton, David S Browning, Robert L Carter, Leonardo Dagum, Rod A Fatoohi, Paul O Frederickson, Thomas A Lasinski, Rob S Schreiber, et al. 1991. The NAS parallel benchmarks. The International Journal of Supercomputing Applications 5, 3 (1991), 63-73.

74 references, page 1 of 5
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