In these years of severe chip shortage, it is even more important to improve the efficiency of chip manufacturing. As is well known, manufacturing phases rely on increasingly intelligent production machinery, which must ensure high quality and large volumes. That is true also for die-bonding machines, which are required to satisfy very high standards of speed and accuracy. For this purpose, such devices have started to evaluate the possibility of adopting computer vision algorithms for automatic recognition of wafer positioning and die size.This paper proposes an FPGA accelerated implementation of one of these algorithms, demonstrating the advantages of using this technology to this end and paving the way towards a larger adoption of this kind of acceleration platform for the different tasks composing modern industrial motion control systems. At the state of the art, such systems are typically managed with software-oriented solutions, which may not be sufficient in the case of highly restrictive requirements in terms of execution time. For this reason, the design flow considered the use of high-level hardware design, which offers a more software-friendly solution to developers without in-depth hardware knowledge. The proposed solution is a state-of-the-art implementation for execution time and resources of programmable logic while enabling higher precision in terms of die position estimation.