Development of Impedance-Source Inverter Using SiC-MOSFET

Ryuji Iijima; Thilak Senanayake; Takanori Isobe; Hiroshi Tadano

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https://doi.org/10.2...arrow_drop_down

https://doi.org/10.23919/ipec....

Article . 2018 . Peer-reviewed

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https://dx.doi.org/10.23919/ip...

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Development of Impedance-Source Inverter Using SiC-MOSFET

descriptionPublicationkeyboard_double_arrow_right Article , Other literature type 01 May 2018Publisher:IEEEJournal:2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia)

Authors: Ryuji Iijima; Thilak Senanayake; Takanori Isobe; Hiroshi Tadano;

doi: 10.23919/ipec.2018.8507561

Development of Impedance-Source Inverter Using SiC-MOSFET

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Abstract

Impedance-source inverter using SiC-MOSFET was studied. A 3-kW laboratory level inverter had the efficiency of about 96 % at the condition of output boost ratio G of 1.77 (boost ratio B of 2.5), output power of 3.16 kW and input voltage of 240 V. At lower G case of 1.32 (B of 1.61), the efficiency of impedance-source inverter was increased by 97.4 % due to low conduction loss of SiC-MOSFET.

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University of Tsukuba
Japan

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