CMOS image sensors are being used in an increasing number of low power and low cost applications. This is mainly due to the use of standard CMOS technology which allows for the realization of image capture devices as well as processing circuitry on a single chip. In addition, the increased integration density, offered in nowadays advanced CMOS technologies, has opened the door to the implementation of more processing and pixel level data converters, leading to the Digital Pixel Sensor (DPS). On one hand, in DPS architecture, very low speed converters can be used and a high level of parallelism is obtained using ADCs operating at only tens of samples per second. On the other hand, DPS suffers from reduced fill-factor of the image sensor since a significant part of the pixel area is dedicated to the ADC circuitry. In addition, DPS designers need to address most CMOS imagers design challenges such as power consumption, Signal-to-Noise Ratio (SNR) and Dynamic Range (DR). In this thesis, we propose a time domain DPS which encodes the photocurrent in the pulse width of the signal. This is achieved by integrating the same amount of charges for all pixels, regardless of their illuminations, by fixing the integration voltage instead of fixing the integration time as most CMOS imagers do. A 100dB dynamic range is proven to be achievable. In addition, as information is encoded in the pulse width, only a single transition is required for each pixel; keeping the power to a minimum level when compared to a Pulse Frequency Modulation (PFM) scheme. In this thesis, we first present a Pulse Width Modulation (PWM) based DPS, which is used as a proof-of-concept prototype. Experimental results show the successful operation of the proposed architecture. A second generation sensor based on an improved PWM self-resetting scheme is then proposed making use of only 16 transistors as compared to 20 transistors used in the first generation prototype. The fill-factor is also improved from 13% to 20%. The pixel array is reconfigurable so ...