publication . Article . 2020

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Riduan Khaddam-Aljameh; Pier Andrea Francese; Luca Benini; Evangelos Eleftheriou;
Open Access
  • Published: 10 Dec 2020 Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, volume 29, pages 372-385 (issn: 1063-8210, eissn: 1557-9999, Copyright policy)
  • Publisher: Institute of Electrical and Electronics Engineers (IEEE)
A novel interleaved switched-capacitor and SRAM-based multibit matrix-vector multiply-accumulate engine for in-memory computing is presented. Its operation principle is based on first converting an SRAM-stored n-bit weight into a proportional voltage using a pipeline D/A converter built from $n+1$ equally sized stages. A switched-capacitor stage then multiplies these voltages with an m-bit digital input activation. Finally, the output voltages that correspond to the different multiplication results are accumulated along one column by means of charge-sharing. With our proposed architecture, the required circuit area, computation time, and power consumption scale ...
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free text keywords: Electrical and Electronic Engineering, Hardware and Architecture, Software, Computer science, Static random-access memory, Operand, Energy consumption, Capacitor, law.invention, law, Multiplier (economics), Computation, Voltage, Topology, Multiplication
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