FPGA‐based parallel process for Walsh–Hadamard transform
Copyright policy ) R. Reynoso‐Godinez; C. Rodriguez‐Donate; M. Lopez‐Ramirez; F.M. Garcia‐Guevara;
FPGA‐based parallel process for Walsh–Hadamard transform
A field‐programmable gate array‐based reconfigurable parallel computing unit to calculate the Walsh–Hadamard transform is proposed. The architecture can process long‐duration signals with a large number of samples. Obtained results demonstrate its versatility and usefulness in applications requiring online digital signal processing, utilising few resources in low‐cost devises as Cyclone II 2C20 and Cyclone IV EP4CE22.
- Universidad de Guanajuato Mexico
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selected citations
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These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
Citations provided by BIP!popularityPopularity provided by BIP!
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
Popularity provided by BIP! 5
Top 10%
Average
Average
gold