To be able to implement large-scale SOC designs, minimizing overall power dissipation is a critical. The primary objective of this chapter is to present the results of silicon nanowire technology in a widely utilized prototyping platform called Field-Programmable Gate Array (FPGA). The proposed FPGA architecture in this chapter uses cluster blocks, each of which includes several Look-Up-Tables (LUT) to configure any logic functionality. Each LUT can be configured as a combinatorial logic block or part of a state machine. This flexible configuration is achieved by scan chains implemented inside the cluster block to define the interconnectivity between LUTs and to determine the logic functionality for each LUT. After describing the architectural aspects of the LUT and the cluster, circuit simulations were performed using BSIMSOI SNT models. The chapter reports the results of worst-case propagation delays and power dissipation figures of various FPGA circuits and shows typical LUT and the cluster layouts.