descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Article 01 Jan 1988Publisher:Springer New YorkJournal:Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference

Authors: R.B. Garner; A. Agrawal; David A. Patterson; Steve Kleiman; F. Briggs; B. Joy; D. Hough; +5 Authors

doi: 10.1007/978-1-4612-3192-9_2 , 10.1109/cmpcon.1988.4874

The Scalable Processor Architecture (SPARC)

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Abstract

An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided. >

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University of California, Berkeley
United States

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