The subgraph isomorphism problem has various important applications, although it is generally NP-complete and difficult to solve. This paper examines the feasibility of a data dependent circuit for the subgraph isomorphism problem, which is particularly suitable for FPGA implementation. For graphs of 32 vertices, the average logic scale of data dependent circuits is only 5% of the corresponding data independent circuit. The circuit is estimated to be 460 times faster than the software for 32 vertices. Even if the circuit generation time is included, a data dependent circuit is expected to be two times faster than software when there are 32 vertices. For larger graphs, the performance gain would be far larger.