AbstractWe have proposed a hierarchical built‐in self‐test (BIST) mechanism for register‐transfer level (RTL) circuits, to simplify testing design methods. Hierarchical BIST is a two‐layered approach to BIST that operates at the register‐transfer level and gate level. At the register‐transfer level, the test‐pattern generator creates a test pattern and applies it to the module under test, and creates a pathway that enables the response analyzer to monitor the results. At the gate level, the error‐detection rate for the module under test is tested by simulating errors. An advantage of the hierarchical BIST approach is that high detection rates can be achieved with low hardware overhead. In this paper, we propose time‐division single‐control testability as a testability model for hierarchical BIST. We conducted tests that demonstrate this is an effective way to reduce test execution time and hardware overhead. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(6): 47–58, 2007; Published online in Wiley InterScience (www.interscience.wiley. com). DOI 10.1002/ecjb.20362