publication . Article . 2014

Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology

Firlej, M; Fiutowski, T; Idzik, M; Moron, J; Swientek, K;
Open Access English
  • Published: 01 Jan 2014
  • Publisher: JINST
Abstract
The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz–3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz–1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO ...
Subjects
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_PERFORMANCEANDRELIABILITYHardware_ARITHMETICANDLOGICSTRUCTURES
free text keywords: Detectors and Experimental Techniques, Microelectronics and interconnection technology [3], 3D Interconnection [3.2]
Funded by
EC| AIDA
Project
AIDA
Advanced European Infrastructures for Detectors at Accelerators
  • Funder: European Commission (EC)
  • Project Code: 262025
  • Funding stream: FP7 | SP4 | INFRA
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