publication . Preprint . 2018

A Scalable Approach for Hardware Semiformal Verification

Grimm, Tomas; Lettnin, Djones; Hübner, Michael;
Open Access English
  • Published: 22 Jan 2018
The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation and FPGA prototyping. However, none is able to verify a complete architecture. Furthermore, hybrid approaches aiming at complete verification use techniques that lower the overall complexity by increasing the abstraction level. This work focuses on the verification of complex systems at the RT level to handle the hardware peculiarities. Our results show an improvement of 100\% compared to the commercial tool's results for the prototype we used to validate our approach.
free text keywords: Computer Science - Logic in Computer Science, Computer Science - Software Engineering
Related Organizations
Download from

[1] ITRS, “International Technology Roadmap for Semiconductors 2.0,” Tech. Rep., 2015.

[2] J. Turley, “Avoiding the SoC Verification Iceberg,” 2013. [Online]. Available:

[3] H. Foster, “Trends in functional verification,” in Proceedings of the 52nd Annual Design Automation Conference (DAC '15). New York, New York, USA: ACM Press, 2015, pp. 1-6.

[4] V. Singhal, “Oski Technologies-Formal Verification: Theory and Practice.” [Online]. Available: deepakd/ talks/formal-iisc-0306.pdf

[5] A. Cimatti and et al., “Software Model Checking SystemC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 5, pp. 774-787, 2013.

[6] E. Seligman, T. Schubert, and M. V. A. K. Kumar, Formal verification: an essential toolkit for modern VLSI design. Morgan Kaufmann, 2015. [OpenAIRE]

[7] D. Gajski and et al., Embedded System Design. Boston, MA: Springer US, 2009.

[8] D. Nenni and D. Dingee, Prototypical - The Emergence of FPGA-Based Prototyping for SoC Design. CreateSpace Independent Publishing Platform, 2016.

[9] U. Simm, S. Rosenberg, E. de Kock, and P. A. Hartmann, “Accellera Standards Technical Update,” in 2015 Design and Verification Conference and Exhibition, 2015.

[10] H. Foster, “Applied Assertion-Based Verification: An Industry Perspective,” Foundations and Trends R in Electronic Design Automation, vol. 3, no. 1, pp. 1-95, 2009.

[11] R. Mukherjee and et al., “Hardware Verification Using Software Analyzers,” in 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE, jul 2015, pp. 7-12.

[12] P. Herber, “The RESCUE Approach - Towards Compositional Hardware/Software Co-verification,” in 2014 IEEE Intl Conf on High Performance Computing and Communications (HPCC). IEEE, aug 2014, pp. 721-724.

[13] D. Große and et al., “HW/SW co-verification of embedded systems using bounded model checking,” in Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06. New York, New York, USA: ACM Press, 2006, p. 43.

Powered by OpenAIRE Research Graph
Any information missing or wrong?Report an Issue