publication . Conference object . Preprint . 2019

Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance

Daniel Hackenberg; Mario Bielert; Andreas Gocht; Thomas Ilsche; Robert Schöne;
Open Access
  • Published: 28 May 2019
  • Publisher: IEEE
Abstract
Comment: 8 pages, HPCS2019, HPBench, READEX, HAEC, Horizon2020, H2020 grant agreement number 671657, DFG, CRC 912
Subjects
free text keywords: Computer Science - Distributed, Parallel, and Cluster Computing, x86, 512-bit, Uncore, Embedded system, business.industry, business, Dynamic voltage scaling, Systems modeling, Supercomputer, Efficient energy use, Computer science, Bandwidth throttling
Related Organizations
Funded by
EC| READEX
Project
READEX
Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing
  • Funder: European Commission (EC)
  • Project Code: 671657
  • Funding stream: H2020 | RIA
Communities
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing
20 references, page 1 of 2

[4] R. Schöne, T. Ilsche, M. Bielert, D. Molka, and D. Hackenberg, “Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors,” in Proceedings of the 4th International Workshop on Energy Efficient Supercomputing (E2SC), 2016, DOI: 10.1109/E2SC.2016.15.

[5] B. Rountree, D. H. Ahn, B. R. de Supinski, D. K. Lowenthal, and M. Schulz, “Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound,” in 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum, 2012, DOI: 10.1109/IPDPSW.2012.116.

[6] K. Lange, “Identifying Shades of Green: The SPECpower Benchmarks,” Computer, 2009, DOI: 10.1109/MC.2009.84.

[7] J. Bucek, K.-D. Lange, and J. v. Kistowski, “SPEC CPU2017: Next-Generation Compute Benchmark,” in Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, DOI: 10.1145/3185768.3185771.

[8] A. Fog, “The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers,” online, Technical University of Denmark, Sep 2018. [Online]. Available: http://agner.org/optimize/microarchitecture.pdf

[9] N. Kurd, M. Chowdhury, E. Burton, T. Thomas, C. Mozak, B. Boswell, M. Lal et al., “Haswell: A family of IA 22nm processors,” in IEEE International Solid - State Circuits Conference - (ISSCC), 2014, DOI: 10.1109/ISSCC.2014.6757361.

[10] B. Bowhill, B. Stackhouse, N. Nassif, Z. Yang, A. Raghavan, C. Morganti et al., “The xeon® processor e5-2600 v3: A 22nm 18-core product family,” in IEEE International Solid-State Circuits Conference - (ISSCC), 2015, DOI: 10.1109/ISSCC.2015.7062934.

[11] Intel 64 and IA-32 Architectures Optimization Reference Manual, Intel, Apr 2018, order Number: 248966-040. [Online]. Available: https://software.intel.com/sites/default/files/managed/9e/bc/ 64-ia-32-architectures-optimization-manual.pdf

[12] S. M. Tam, H. Muljono, M. Huang, S. Iyer, K. Royneogi, N. Satti, R. Qureshi et al., “SkyLake-SP: A 14nm 28-Core Xeon Processor,” in IEEE International Solid - State Circuits Conference - (ISSCC), DOI: 110.1109/ISSCC.2018.8310170.

[13] “Intel Xeon Processor Scalable Family Technical Overview,” Jul 2017. [Online]. Available: https://software.intel.com/en-us/articles/ intel-xeon-processor-scalable-family-technical-overview

[14] A. Mazouz, A. Laurent, B. Pradelle, and W. Jalby, “Evaluation of CPU Frequency Transition Latency,” Computer Science - Research and Development, 2014, DOI: 10.1007/s00450-013-0240-x.

[15] “Advanced configuration and power interface (acpi) specification, revision 6.3,” Jan. 2018, online at uefi.org (accessed 2019-03-27).

[16] T. Ilsche, R. Schöne, P. Joram, M. Bielert, and A. Gocht, “System Monitoring with lo2s: Power and Runtime Impact of C-State Transitions,” in IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, DOI: 10.1109/IPDPSW.2018.00114.

[17] Energy Efficient Servers: Blueprints for Data Center Optimization.

[18] D. Hackenberg, R. Oldenburg, D. Molka, and R. Schöne, “Introducing FIRESTARTER: A processor stress test utility,” in International Green Computing Conference (IGCC), 2013, DOI: http://dx.doi.org/10.1109/IGCC.2013.6604507. [OpenAIRE]

20 references, page 1 of 2
Abstract
Comment: 8 pages, HPCS2019, HPBench, READEX, HAEC, Horizon2020, H2020 grant agreement number 671657, DFG, CRC 912
Subjects
free text keywords: Computer Science - Distributed, Parallel, and Cluster Computing, x86, 512-bit, Uncore, Embedded system, business.industry, business, Dynamic voltage scaling, Systems modeling, Supercomputer, Efficient energy use, Computer science, Bandwidth throttling
Related Organizations
Funded by
EC| READEX
Project
READEX
Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing
  • Funder: European Commission (EC)
  • Project Code: 671657
  • Funding stream: H2020 | RIA
Communities
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing
20 references, page 1 of 2

[4] R. Schöne, T. Ilsche, M. Bielert, D. Molka, and D. Hackenberg, “Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors,” in Proceedings of the 4th International Workshop on Energy Efficient Supercomputing (E2SC), 2016, DOI: 10.1109/E2SC.2016.15.

[5] B. Rountree, D. H. Ahn, B. R. de Supinski, D. K. Lowenthal, and M. Schulz, “Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound,” in 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum, 2012, DOI: 10.1109/IPDPSW.2012.116.

[6] K. Lange, “Identifying Shades of Green: The SPECpower Benchmarks,” Computer, 2009, DOI: 10.1109/MC.2009.84.

[7] J. Bucek, K.-D. Lange, and J. v. Kistowski, “SPEC CPU2017: Next-Generation Compute Benchmark,” in Companion of the 2018 ACM/SPEC International Conference on Performance Engineering, DOI: 10.1145/3185768.3185771.

[8] A. Fog, “The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers,” online, Technical University of Denmark, Sep 2018. [Online]. Available: http://agner.org/optimize/microarchitecture.pdf

[9] N. Kurd, M. Chowdhury, E. Burton, T. Thomas, C. Mozak, B. Boswell, M. Lal et al., “Haswell: A family of IA 22nm processors,” in IEEE International Solid - State Circuits Conference - (ISSCC), 2014, DOI: 10.1109/ISSCC.2014.6757361.

[10] B. Bowhill, B. Stackhouse, N. Nassif, Z. Yang, A. Raghavan, C. Morganti et al., “The xeon® processor e5-2600 v3: A 22nm 18-core product family,” in IEEE International Solid-State Circuits Conference - (ISSCC), 2015, DOI: 10.1109/ISSCC.2015.7062934.

[11] Intel 64 and IA-32 Architectures Optimization Reference Manual, Intel, Apr 2018, order Number: 248966-040. [Online]. Available: https://software.intel.com/sites/default/files/managed/9e/bc/ 64-ia-32-architectures-optimization-manual.pdf

[12] S. M. Tam, H. Muljono, M. Huang, S. Iyer, K. Royneogi, N. Satti, R. Qureshi et al., “SkyLake-SP: A 14nm 28-Core Xeon Processor,” in IEEE International Solid - State Circuits Conference - (ISSCC), DOI: 110.1109/ISSCC.2018.8310170.

[13] “Intel Xeon Processor Scalable Family Technical Overview,” Jul 2017. [Online]. Available: https://software.intel.com/en-us/articles/ intel-xeon-processor-scalable-family-technical-overview

[14] A. Mazouz, A. Laurent, B. Pradelle, and W. Jalby, “Evaluation of CPU Frequency Transition Latency,” Computer Science - Research and Development, 2014, DOI: 10.1007/s00450-013-0240-x.

[15] “Advanced configuration and power interface (acpi) specification, revision 6.3,” Jan. 2018, online at uefi.org (accessed 2019-03-27).

[16] T. Ilsche, R. Schöne, P. Joram, M. Bielert, and A. Gocht, “System Monitoring with lo2s: Power and Runtime Impact of C-State Transitions,” in IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, DOI: 10.1109/IPDPSW.2018.00114.

[17] Energy Efficient Servers: Blueprints for Data Center Optimization.

[18] D. Hackenberg, R. Oldenburg, D. Molka, and R. Schöne, “Introducing FIRESTARTER: A processor stress test utility,” in International Green Computing Conference (IGCC), 2013, DOI: http://dx.doi.org/10.1109/IGCC.2013.6604507. [OpenAIRE]

20 references, page 1 of 2
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