27 references, page 1 of 2
[1] Chipworks, “Intel's 22-nm Tri-gate Transistors Exposed.” http://www.chipworks.com/en/technical-competitive-analysis/resources/ blog/intels-22-nm-tri-gate-transistors-exposed/, Apr. 2012.
[2] Chipworks, “Reverse Engineering Software.” http://www.chipworks.com/ en/technical-competitive-analysis/resources/reerse-engineering-software. Last accessed May 2014.
[3] Degate, “Reverse engineering integrated circuits with degate.” http://www. degate.org/documentation/. Last accessed May 2014.
[4] Chipworks, “Inside the Apple Lightning Cable.” http://www. chipworks.com/en/technical-competitive-analysis/resources/blog/ inside-the-apple-lightning-cable/, Oct. 2012.
[5] SypherMedia, “Syphermedia library circuit camouflage technology.” http: //www.smi.tv/solutions.htm. Last accessed May 2014.
[6] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” in Proceedings of the 2013 ACM SIGSAC Conference on Computer and Communications Security, CCS '13, (New York, NY, USA), pp. 709-720, ACM, 2013.
[7] J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold cmos technology,” in Proceedings of the 34th annual Design Automation Conference, pp. 409-414, ACM, 1997.
[8] Y. Huang, C. Williams, and H. Smith, “Direct comparison of crosssectional scanning capacitance microscope dopant profile and vertical secondary ion-mass spectroscopy profile,” Journal of Vacuum Science & Technology B, vol. 14, no. 1, pp. 433-436, 1996.
[9] R. Torrance and D. James, “Reverse engineering in the semiconductor industry,” in Custom Integrated Circuits Conference, 2007. CICC'07. IEEE, pp. 429-436, IEEE, 2007.
[10] L. Sekanina, R. Ruzicka, Z. Vasicek, R. Prokop, and L. Fujcik, “Repomo32-new reconfigurable polymorphic integrated circuit for adaptive hardware,” in Evolvable and Adaptive Hardware, 2009. WEAH'09. IEEE Workshop on, pp. 39-46, IEEE, 2009. [OpenAIRE]
[11] A. Stoica, R. Zebulum, and D. Keymeulen, Polymorphic electronics. Springer, 2001.
[12] R. Ruzicka, L. Sekanina, and R. Prokop, “Physical demonstration of polymorphic self-checking circuits,” in On-Line Testing Symposium, 2008. IOLTS'08. 14th IEEE International, pp. 31-36, IEEE, 2008.
[13] A. Stoica, R. Zebulum, D. Keymeulen, and J. Lohn, “On polymorphic circuits and their design using evolutionary algorithms,” in In: Proc. of IASTED International Conference on Applied Informatics AI2002, Insbruck, Citeseer, 2002.
[14] L. Larson, “Convertible multi-function microelectronic logic gate structure and method of fabricating the same,” Sept. 8 1992. US Patent 5,146,117.
[15] R. Walden, “Dynamic circuit disguise for microelectronic integrated digital logic circuits,” Apr. 13 1993. US Patent 5,202,591.
27 references, page 1 of 2