publication . Other literature type . Preprint . Article . 2015

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Gage Hills; null Jie Zhang; Max Marcel Shulaker; null Hai Wei; null Chi-Shuen Lee; Arjun Balasingam; H.-S Philip Wong; Subhasish Mitra;
  • Published: 20 Jul 2015
  • Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper,...
Subjects
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_LOGICDESIGNHardware_PERFORMANCEANDRELIABILITY
free text keywords: Computer Science - Emerging Technologies, Circuit delay, Electrical engineering, business.industry, business, Transistor, law.invention, law, Carbon nanotube, Standard cell, Electronic engineering, Logic gate, Noise margin, Computer science, Circuit design, Sizing
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publication . Other literature type . Preprint . Article . 2015

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Gage Hills; null Jie Zhang; Max Marcel Shulaker; null Hai Wei; null Chi-Shuen Lee; Arjun Balasingam; H.-S Philip Wong; Subhasish Mitra;