publication . Conference object . Preprint . 2018

Full wafer redistribution and wafer embedding as key technologies for a multi-scale neuromorphic hardware cluster

Zoschke, Kai; Güttler, M.; Böttcher, L.; Grübl, A.; Husmann, D.; Schemmel, J.; Meier, K.-H.; Ehrmann, O.;
Open Access
  • Published: 15 Jan 2018
  • Publisher: IEEE
  • Country: Germany
Abstract
Comment: Accepted at EPTC 2017
Subjects
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_PERFORMANCEANDRELIABILITY
free text keywords: Optoelectronics, business.industry, business, Electrical connection, Neuromorphic engineering, Electronic engineering, Etching, Wafer-level packaging, Lithography, Materials science, Reticle, Wafer, Printed circuit board, Computer Science - Emerging Technologies, Computer Science - Neural and Evolutionary Computing
Funded by
EC| BRAINSCALES
Project
BRAINSCALES
Brain-inspired multiscale computation in neuromorphic hybrid systems
  • Funder: European Commission (EC)
  • Project Code: 269921
  • Funding stream: FP7 | SP1 | ICT
,
EC| HBP SGA1
Project
HBP SGA1
Human Brain Project Specific Grant Agreement 1
  • Funder: European Commission (EC)
  • Project Code: 720270
  • Funding stream: H2020 | SGA-RIA
,
EC| HBP
Project
HBP
The Human Brain Project
  • Funder: European Commission (EC)
  • Project Code: 604102
  • Funding stream: FP7 | SP1 | ICT
Communities
FET FP7FET Proactive: FET proactive 8: Brain Inspired ICT
FET FP7FET Proactive: Brain-inspired multiscale computation in neuromorphic hybrid systems
FET FP7FET Flagships: FET Flagships
FET FP7FET Flagships: The Human Brain Project

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2. S. Millner, A. Grübl, K. Meier, J. Schemmel, and M.-O. Schwartz, “A VLSI implementation of the adaptive exponential integrate-and-fire neuron model,” in Advances in Neural Information Processing Systems 23, J. Lafferty, C. K. I. Williams, J. Shawe-Taylor, R. Zemel, and A. Culotta, Eds., 2010, pp. 1642-1650. [OpenAIRE]

3. J. Schemmel, D. Brüderle, A. Grübl, M. Hock, K. Meier, and S. Millner, “A wafer-scale neuromorphic hardware system for large-scale neural modeling,” in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1947-1950. [OpenAIRE]

4. S. Friedmann, J. Schemmel, A. Grübl, A. Hartel, M. Hock, and K. Meier, “Demonstrating hybrid learning in a flexible neuromorphic hardware system,” IEEE Transactions on Biomedical Circuits and Systems, vol. 11, no. 1, pp. 128- 142, 2017. [OpenAIRE]

5. J. Schemmel, L. Kriener, P. Müller, and K. Meier, (2017), “An Accelerated Analog Neuromorphic Hardware System Emulating NMDA-and Calcium-Based Non-Linear Dendrites. arXiv preprint arXiv:1703.07286, 2017. [OpenAIRE]

6. M. Töpper, “Wafer Level Chip Scale Packaging” Materials for Advanced Packaging, ISBN: 978-3-319- 45097-1, pp 627-695

7. S. Qu, Y. Liu, Wafer-Level Chip-Scale Packaging, ISBN 978-1-4939-1556-9, pp 15-38

8. Hannes Stahr, Mark Beesley, “Embedded Components on the way to Industrialization”, SMTA International Conference, Ft. Worth/USA, October 16 - 20, 2011

9. Human Brain Project SP9 Partners, “Neuromorphic Platform Specification”, 2014

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publication . Conference object . Preprint . 2018

Full wafer redistribution and wafer embedding as key technologies for a multi-scale neuromorphic hardware cluster

Zoschke, Kai; Güttler, M.; Böttcher, L.; Grübl, A.; Husmann, D.; Schemmel, J.; Meier, K.-H.; Ehrmann, O.;