Symmetric Logic Synthesis with Phase Assignment

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Benschop, N. F.;
  • Subject: Mathematics - General Mathematics | 94C10, 06E30, 05E05

Decomposition of any Boolean Function BF_n of n binary inputs into an optimal inverter coupled network of Symmetric Boolean functions SF_k (k \leq n) is described. Each SF component is implemented by Threshold Logic Cells, forming a complete and compact T-Cell Library. ... View more
  • References (9)

    1. S. Akers: ”Binary Decision Diagrams”, IEEE Comp. C-27, 509-516, June 1978

    2. R. Bryant: ”Graph-based algorithms for Boolean function manipulation”, IEEE Comp. C-35, 677-691, Aug 1986

    3. L. Heinrich-Litan, P. Molitor: ”Least Upper Bounds for the size of OBDDs using Symmetry Principles”, IEEE Comp. C-49, 360-8, Apr 2000

    4. J. v.Eijndhoven: ”CMOS cell generation for Logic Synthesis”, proc. ASICON'94, 75-78, W.Y.Yuan (Ed) Beijing, Oct 1994.

    5. T. Courtney, ”Multiplexer based reconfiguration for Virtex multipliers”, FieldProgrammable Logic and Applications, FPL2000, 749-758, Villach, Austria, Aug 2000.

    6. G. Muurling: ”Fault tolerance in IC design using error correcting codes”, MSc thesis TU-Delft, July 2000.

    7. G. Muurling, ”Error correction for combinational logic circuits”, Benelux 21-st Symposium on Information Theory, 25-31, Wassenaar, May 2000.

    8. R. Kleihorst, N. Benschop: ”Experiments with fault tolerant IC design using error correcting codes”, International Online Testing workshop, Sicily, July 2001.

    9. N. Benschop: ”The structure of Constant Rank State Machines”, Logic and Architecture Synthesis, 167-176, G.Saucier (Ed.) Paris, May 1990 (North-Holland, 1991)

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