publication . Conference object . 2008

Runtime adaptive multi-processor system-on-chip: RAMPSoC

Göhringer, D.; Hübner, M.; Schatz, V.; Becker, J.;
Restricted
  • Published: 01 Jan 2008 Journal: 2008 IEEE International Symposium on Parallel and Distributed Processing (issn: 1530-2075, Copyright policy)
  • Publisher: IEEE
  • Country: Germany
Abstract
Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized ...
Subjects
free text keywords: multiprocessor system, reconfigurable hardware, FPGA, run-time adaptive system, Microprocessor, law.invention, law, System on a chip, MPSoC, Systems design, Supercomputer, Electronic design automation, Computer architecture, Parallel computing, Control reconfiguration, Computer science, Reconfigurable computing
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publication . Conference object . 2008

Runtime adaptive multi-processor system-on-chip: RAMPSoC

Göhringer, D.; Hübner, M.; Schatz, V.; Becker, J.;