VHDL Implementation of a Fast Adder Tree

Bachelor thesis English OPEN
Dacheng, Chen;
  • Publisher: Institutionen för systemteknik
  • Subject: add tree | Elektroteknik | Wallace tree | simulation | cell array | generator | Electrical engineering | counter module

This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem. The basic research has been carried out by MATLAB programming environment and automatic generati... View more
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