3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Other literature type, Conference object English OPEN
G. Beanato; I. Loi; G. De Micheli; Y. Leblebici; L. Benini;
  • Publisher: IEEE Press
  • Related identifiers: doi: 10.1109/VLSI-SoC.2012.6379001
  • Subject: clocks | through-silicon vias | joining processes | memory management | L1 memories | Multi-Core Clusters | network architecture | decoding | integrated circuit interconnections | stacking
    acm: Hardware_MEMORYSTRUCTURES

Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the archi... View more
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