publication . Conference object . 2005

International Collaboration in Packaging Education: Hands-on System-on-Package (SOP) Graduate Level Courses at Indian Institute of Science and Georgia Tech PRC

Varadarajan, Mahesh; Bhattacharya, Swapan; Doraiswami, Ravi; Rao, Ananda G; Rao, NJ; May, Gary; Conrad, Leyla; Tummala, Rao;
Open Access
  • Published: 01 Jan 2005
  • Publisher: IEEE
  • Country: India
System-on-Package (SOP) continues to revolutionize the realization of convergent systems in microelectronics packaging. The SOP concept which began at the Packaging Research Center (PRC) at Georgia Tech has benefited its international collaborative partners in education including the Indian Institute of Science (IISc). The academic program for electronics packaging currently in the Centre for Electronics Design and Technology (CEDT) at IISc is aimed at educating a new breed of globally-competitive engineers in the new SOP technology to meet the next generation workforce need of global as well as the Indian electronics industry. This has been possible with the ha...
ACM Computing Classification System: ComputingMilieux_COMPUTERSANDEDUCATION
free text keywords: Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Related Organizations

1. Tummala Rao R., “SOP: What is it and why? A new microsytem-integration technology paradigm- Moore's law for system integration of miniaturized convergent sytems of the next decade”, IEEE Transactions on Advanced Packaging, Vol 27, No.2, May 2004.

2. Information Technology Annual Report 2003-04, Published by the Ministry of Communication and Information Technology, Government of India, 2004.

3. Mahesh Varadarajan, Joseph M. Hobbs, Orfi Sanchez, Swapan K. Bhattacharaya, Rao R. Tummala, Gary S. May, “A Hands-on Multi-disciplinary Product Development Course for Micro Systems Packaging Education at Georgia Tech.”, Proc 51th Electronic Components and Technology Conf, Orlando, FL, May. 2001, pp.405.

4. Doraiswami, R.; Jing Li; Bhattacharya, S.K.; Conrad, L.; May, G.S.; Tummala, R.R., “Hands-on module packaging education at Georgia Tech” Proc 52nd Electronic Components and Technology Conf, San Diego, CA, May 2002, pp 1517.

5. Ananda Rao G and Rao N J., “A web based course on designing high density interconnect PCBs for manufacturability”, Proc 50th Electronic Components and Technology Conf, Las Vegas, NV, 2000, pp 1285. [OpenAIRE]

6. Paul Wesling, “Electronics Packaging Education: NSF and IEEE initatiatives and Modules”, Proc 51th Electronic Components and Technology Conf, Orlando, FL, May. 2001, pp. 388

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