publication . Conference object . 2017

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini;
Open Access English
  • Published: 16 Nov 2017
  • Publisher: IEEE
  • Country: Italy
Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultra-low-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced technology nodes. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to efficiently compensate, at run-time, these variations. The proposed method exploits on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with on-chip low-power Body Bias Generators. We characterize the response of the PMBs versus the maximum achievable frequency of the system, deriving a predictive model able to estimate such frequency with an error of 3%. We apply this model to compensate Temperature-induced performance variations, estimating the maximum frequency with an error of 7%; we eliminate the error by adding an appropriate body-bias margin resulting in a worst case global power consumption overhead of 5%. As further improvement, we generalize the methodology to compensate also process variations, obtaining an error of 28% on the estimated maximum performance and compensating this error with an overhead of 17% on the global power consumption.
Persistent Identifiers
free text keywords: embedded systems, integrated circuit design, integrated circuit reliability, low-power electronics, power aware computing, silicon-on-insulator, Computer science, Silicon on insulator, Reliability (semiconductor), Compensation (engineering), Process (computing), Multi-core processor, Sensitivity (control systems), Range (statistics), Overhead (computing), Electronic engineering
Funded by
EC| ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
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