Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Conference object English OPEN

Di Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, Luca;

(2017)

Related identifiers: doi: 10.1109/PATMOS.2017.8106979
Subject: embedded systems, integrated circuit design, integrated circuit reliability, low-power electronics, power aware computing, silicon-on-insulator

Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultra-low-power (ULP) devices tha... View more

Similar Research Results (3)

An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits (2008)	89%
Energy Efficient Distributed-Oscillators at 134 and 202GHz with Phase-Noise Optimization through Body-Bias Control in 28nm CMOS FDSOI Technology (2017)	83%
Combined analysis of supply voltage and body-bias voltage for energy management (2018)	75%

Metrics
No metrics available

Share - Bookmark

Download from
Archivio istituzionale della ricerca - Alma Mater Studiorum Università di Bologna via Archivio istituzionale della ricerca - Alma Mater Studiorum Università di Bologna (Conference object, 2017)
Funded by
EC| ExaNoDe
Related to
FET H2020-> FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020-> FET HPC: European Exascale Processor Memory Node Design
Cite this publication