publication . Contribution for newspaper or weekly magazine . Conference object . 2018

Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems

Przemyslaw Mroszczyk; Vasilis F. Pavlidis;
Open Access English
  • Published: 18 May 2018
  • Country: United Kingdom
Abstract
This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4∗ higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.
Persistent Identifiers
Subjects
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_PERFORMANCEANDRELIABILITY
free text keywords: 2.5-D integration, I/O design, Low swing, digital trimming, mismatch cancellation, passive interposer, /dk/atira/pure/subjectarea/asjc/1700/1708, Hardware and Architecture, /dk/atira/pure/subjectarea/asjc/2200/2208, Electrical and Electronic Engineering, /dk/atira/pure/subjectarea/asjc/2200/2213, Safety, Risk, Reliability and Quality, Computer science, Interposer, Swing, Single-ended signaling, Transmitter, Transceiver, Compensation (engineering), CMOS, Electrical engineering, business.industry, business, Electronic circuit
Related Organizations
Funded by
EC| ExaNoDe
Project
ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
Validated by funder
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