Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Contribution for newspaper or weekly magazine English OPEN
Mroszczyk, Przemyslaw ; Pavlidis, Vasileios (2018)
  • Related identifiers: doi: 10.1109/ISCAS.2018.8351057
  • Subject:
    arxiv: Computer Science::Hardware Architecture | Computer Science::Emerging Technologies

Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.
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