publication . Conference object . Contribution for newspaper or weekly magazine . 2018

Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Przemyslaw Mroszczyk; Vasilis F. Pavlidis;
Open Access
  • Published: 04 May 2018
  • Publisher: IEEE
  • Country: United Kingdom
Abstract
Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the num...
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Persistent Identifiers

doi: 10.1109/iscas.2018.8351057

Subjects
arXiv: Computer Science::Hardware ArchitectureComputer Science::Emerging Technologies
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITS
free text keywords: Electronic circuit, Wireline, Electronic engineering, Scaling, Optical switch, Computer science, CMOS, Comparator, Transistor, law.invention, law, Inverter
Related Organizations
Funded by
EC| ExaNoDe
Project
ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
Validated by funder
Communities
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: European Exascale Processor Memory Node Design
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The University of Manchester - Institutional Repository
Contribution for newspaper or weekly magazine . 2018
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