publication . Conference object . 2017

Performance Impact of a Slower Main Memory - A case study of STT-MRAM in HPC

Asifuzzaman, Kazi; Pavlovic, Milan; Radulovic, Milan; Zaragoza, David; Kwon, Ohseong; Ryoo, Kyung-Chang; Radojkovic, Petar;
Open Access
  • Published: 04 May 2017
  • Country: Spain
In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that t...
Persistent Identifiers
ACM Computing Classification System: Hardware_MEMORYSTRUCTURESHardware_GENERAL
free text keywords: :Enginyeria electrònica [Àrees temàtiques de la UPC], Processors, High performance, Supercomputers--Programming, Memory--Computer simulation, Processors and memory architectures, Non-volatile memory, Massively parallel and high-performance simulations, STT-MRAM, Main memory, High-performance computing, Ordinadors--Dispositius de memòria, Supercomputadors, :Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], High performance computing, Supercomputers, Computer storage devices, High-performance computing., Càlcul intensiu (Informàtica), Ordinadors -- Dispositius de memòria
Related Organizations
Funded by
EC| ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
Validated by funder
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: European Exascale Processor Memory Node Design
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