publication . Conference object . 2017

Enabling a reliable STT-MRAM main memory simulation

Kazi Asifuzzaman; Rommel Sánchez Verdejo; Petar Radojković;
Open Access English
  • Published: 01 Oct 2017
  • Publisher: Barcelona Supercomputing Center
  • Country: Spain
This work was supported by BSC, Spanish Government through Programa Severo Ochoa (SEV-2015-0493), by the Spanish Ministry of Science and Technology through TIN2015-65316-P project and by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272). This work has also received funding from the European Union's Horizon 2020 research and innovation programme under ExaNoDe project (grant agreement No 671578). The authors wish to thank Terry Hulett, Duncan Bennett and Ben Cooke from Everspin Technologies Inc., for their technical support.
Persistent Identifiers
ACM Computing Classification System: Hardware_MEMORYSTRUCTURES
free text keywords: :Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC], High performance computing, Computer storage devices, STT-MRAM, Main memory, High-performance computing, Càlcul intensiu (Informàtica), Ordinadors -- Dispositius de memòria, :Enginyeria elèctrica [Àrees temàtiques de la UPC], Processors, High performance, Supercomputadors, Magnetoresistive random-access memory, Computer science, Computing with Memory, Unavailability, System-level simulation, Computer architecture, Universal memory, Memory hierarchy, Memory management, Uniform memory access, Computer hardware, business.industry, business
Related Organizations
Funded by
EC| ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
Validated by funder
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: European Exascale Processor Memory Node Design
Any information missing or wrong?Report an Issue