publication . Part of book or chapter of book . Conference object . 2018

HPC Benchmarking: Scaling Right and Looking Beyond the Average

Milan Radulovic; Kazi Asifuzzaman; Paul M. Carpenter; Petar Radojković; Eduard Ayguadé;
Open Access
  • Published: 31 Jul 2018
  • Country: Spain
Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the main performance bottlenecks. In this paper, we execute seven production HPC applications on a production HPC platform, and analyse the key performance bottlenecks: FLOPS performance and memory bandwidth congestion, and the implications on scaling out. We show that the results depend significantly on the number of execution processes and granularity of measurements. We therefore advocate for guidance in the application suites, on selecting the representative scale of the experiments. Also, we propose that the FLOPS performance and memory bandwidth should be represented in terms of the proportions of time with low, moderate and severe utilization. We show that this gives much more precise and actionable evidence than the average.
This work was supported by the Spanish Ministry of Science and Technology (project TIN2015-65316-P), Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), Severo Ochoa Programme (SEV-2015-0493) of the Spanish Government; and the European Union's Horizon 2020 research and innovation programme under ExaNoDe project (grant agreement No 671578).
The final publication is available at Springer via
Peer Reviewed
Persistent Identifiers
free text keywords: :Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC], Parallel processing (Electronic computers), HPC applications, Bottlenecks, FLOPS, Memory bandwidth, Scaling-out, Processament en paral·lel (Ordinadors), Scale (social sciences), Computer science, FLOPS, Distributed computing, Memory bandwidth, Key (cryptography), Production (economics), Scaling, Benchmarking
Funded by
EC| ExaNoDe
European Exascale Processor Memory Node Design
  • Funder: European Commission (EC)
  • Project Code: 671578
  • Funding stream: H2020 | RIA
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