publication . Master thesis . 2009

Parallel-Architecture Simulator Development Using Hardware Transactional Memory

Armejach Sanosa, Adrià;
Open Access English
  • Published: 23 Sep 2009
  • Publisher: Universitat Politècnica de Catalunya
  • Country: Spain
Abstract
To address the need for a simpler parallel programming model, Transactional Memory (TM) has been developed and promises good parallel performance with easy-to-write parallel code. Unlike lock-based approaches, with TM, programmers do not need to explicitly specify and manage the synchronization among threads. However, programmers simply mark code segments as transactions, and the TM system manages the concurrency control for them. TM can be implemented either in software (STM) or hardware (HTM). STMs are more flexible but suffer from serious performance overheads whereas HTMs are faster but limited due to hardware space constrains. We present an implementation of...
Subjects
free text keywords: :Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC], Parallel computers, Computers, Memòria Transaccional, TM, HTM, Programació paral·lela, Maquinari, Transactional Memory, Ordinadors paral·lels, Ordinadors
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