Software trace cache

Article English OPEN
Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo;
(2005)
  • Related identifiers: doi: 10.1109/TC.2005.13
  • Subject: Processament en paral·lel (Ordinadors) | Branch prediction | Trace cache | Memòria ràpida de treball (Informàtica) | Cache memory | Pipeline processors | Compiler optimizations | Compiladors (Programes d'ordinador) | :Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] | Instruction fetch | Compilers (Computer programs) | Parallel processing (Electronic computers)
    acm: Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING | Hardware_MEMORYSTRUCTURES

We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to incre... View more
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