publication . Doctoral thesis . 1992

A study on the effectiveness of lockup-free caches for a Reduced Instruction Set Computer (RISC) processor

Tharpe, Leonard.;
Open Access English
  • Published: 01 Sep 1992
  • Publisher: Monterey, California. Naval Postgraduate School
Approved for public release; distribution is unlimited This thesis presents a simulation and analysis of the Reduced Instruction Set Computer (RISC) architecture and the effects on RISC performance of a lockup-free cache interface. RISC architectures achieve high performance by having a small, but sufficient, instruction set with most instructions executing in one clock cycle. Current RISC performance range from 1.5 to 2.0 CPI. The goal of RISC is to attain a CPI of 1.0. The major hindrance in attaining that goal is attributed to instructions that require main memory access. In this thesis, we attempt to reduce the effects of the high penalties for non-cache acc...
ACM Computing Classification System: Hardware_MEMORYSTRUCTURES
free text keywords: Reduced Instruction Set Computer (RISC), Lockup-free cache interface
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