A study on the effectiveness of lockup-free caches for a Reduced Instruction Set Computer (RISC) processor
- Publisher: Monterey, California. Naval Postgraduate School
Lockup-free cache interface | Reduced Instruction Set Computer (RISC)
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This thesis presents a simulation and analysis of the Reduced Instruction Set Computer (RISC) architecture and the effects on RISC performance of a lockup-free cache interface. RISC architectures achieve high performance by having a small, but sufficient, instruction set with most instructions executing in one clock cycle. Current RISC performance range from 1.5 to 2.0 CPI. The goal of RISC is to attain a CPI of 1.0. The major hindrance in attaining that goal is attributed to instructions that require main memory access. In this thesis, we attempt to reduce the effects of the high penalties for non-cache accesses by using a non-blocking cache memory subsystem called a lockup-free cache. This interface between the cache and main memory prevents the processor from "locking up" when a request from main memory occurs. This is accomplished by entering all non-cache requests into a memory request queue, while the processor continues to issue and execute other instructions. The evaluation of the effects of the lockup-free cache interface is done using different variation of the interface design. The results show that using the lockup-free cache improves the RISC performance.
Captain, United States Army