publication . Conference object . Other literature type . 2016

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid;
Open Access
  • Published: 03 May 2016
Abstract
In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators. H2020 644052 / HECTOR
Funded by
EC| HECTOR
Project
HECTOR
HARDWARE ENABLED CRYPTO AND RANDOMNESS
  • Funder: European Commission (EC)
  • Project Code: 644052
  • Funding stream: H2020 | RIA
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Conference object . 2016
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Other literature type . 2016
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publication . Conference object . Other literature type . 2016

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid;