publication . Conference object . 2020

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Josie E. Rodriguez Condia; Pierpaolo Narducci; M. Sonza Reorda; Luca Sterpone;
Open Access
  • Published: 19 May 2020
  • Publisher: IEEE
  • Country: Italy
Abstract
In the past, in most General-Purpose Graphic Processing Units (GPGPUs) application fields (e.g., multimedia and gaming), the reliability features were not so relevant. Nowadays, GPGPUs are used in new domains, such as the automotive one, where reliability plays a significant role. In this work, we describe a dynamic duplication with a comparison (DDWC) mechanism intended to harden the Scalar Processor (SP) units located in the Streaming multiprocessors (SM) of a GPGPU. The proposed mechanism targets the permanent faults that may arise inside the SPs. One additional SP unit is included in the system to compute redundantly the same operations of a selected SP. Res...
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Subjects
free text keywords: Duplication with Comparison (DWC), Fault detection, General Purpose Graphics Processing Units (GPGPUs), Graphics Processors, Duplication with Comparison (DWC), Fault detection, General Purpose Graphics Processing Units (GPGPUs), Graphics Processors, General-purpose computing on graphics processing units, Hardware redundancy, Redundancy (engineering), Automotive industry, business.industry, business, Control reconfiguration, Computer science, Embedded system, Fault detection and isolation, Latency (engineering), Scalar processor
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Funded by
EC| RESCUE
Project
RESCUE
Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design
  • Funder: European Commission (EC)
  • Project Code: 722325
  • Funding stream: H2020 | MSCA-ITN-ETN
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