The next Generation of Exascale-class Systems: the ExaNeSt Project

Conference object OPEN
R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis; (2017)
  • Related identifiers: doi: 10.5281/zenodo.823594, doi: 10.5281/zenodo.823595
  • Subject: supercomputer | low-latency interconnect | Euratom | rack prototype | non-volatile memory | European Union | real HPC applications | Exascale system | Euratom research & training programme 2014-2018 | Horizon 2020

The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium... View more
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    FET H2020-> FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
    FET H2020-> FET HPC: European Exascale System Interconnect and Storage
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