publication . Conference object . Article . Other literature type . 2017

The Next Generation Of Exascale-Class Systems: The Exanest Project

Roberto Ammendola; Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; P. Paolucci; Elena Pastorelli; Francesco Simula; ...
Open Access
  • Published: 06 Jul 2017
  • Publisher: Zenodo
The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconne...
free text keywords: Exascale system, supercomputer, rack prototype, non-volatile memory, low-latency interconnect, real HPC applications, European Union, Horizon 2020, Euratom, Euratom research & training programme 2014-2018, Euratom research & training programme 2014-2018, Operating system, computer.software_genre, computer, Network topology, Interconnection, Status report, Architecture, Conceptual framework, Field-programmable gate array, Computer science, ARM architecture
Funded by
EC| ExaNeSt
European Exascale System Interconnect and Storage
  • Funder: European Commission (EC)
  • Project Code: 671553
  • Funding stream: H2020 | RIA
Validated by funder
FET H2020FET HPC: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
FET H2020FET HPC: European Exascale System Interconnect and Storage
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Conference object . 2017
Provider: ZENODO
Other literature type . 2017
Provider: Datacite
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