publication . Conference object . 2020

Advanced Hardware Architectures for Turbo Code Decoding Beyond 100 Gb/s

Stefan Weithoffer; Oliver Griebel; Rami Klaimi; Charbel Abdel Nour; Norbert Wehn;
Open Access English
  • Published: 25 May 2020
  • Publisher: IEEE
  • Country: France
International audience; In this paper, we present two new hardware archi-tectures for Turbo Code decoding that combine functional, spatial and iteration parallelism. Our first architecture is the first fully pipelined iteration unrolled architecture that supports multiple frame sizes. This frame flexibility is achieved by providing a set of interleavers designed to achieve a hardware implementation with a reduced routing overhead. The second architecture efficiently utilizes the dynamics of the error rate distribution for different decoding iterations and is comprised of two stages. First, a fully pipelined iteration unrolled decoder stage applied for a predeter...
Persistent Identifiers
free text keywords: Turbo decoder, Forward Error Correction, Fully Parallel, High-throughput, [INFO.INFO-IT]Computer Science [cs]/Information Theory [cs.IT], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [SPI.TRON]Engineering Sciences [physics]/Electronics, Two stages, Computer hardware, business.industry, business, Turbo code, Throughput, Word error rate, Decoding methods, Architecture, Implementation, Computer science
Related Organizations
Funded by
Enabling Practical Wireless Tb/s Communications with Next Generation Channel Coding
  • Funder: European Commission (EC)
  • Project Code: 760150
  • Funding stream: H2020 | RIA
Validated by funder
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