publication . Conference object . Other literature type . Part of book or chapter of book . Preprint . 2016

Flush+Flush: A Fast and Stealthy Cache Attack

Daniel Gruss;
  • Published: 07 Jul 2016
  • Country: France
Research on cache attacks has shown that CPU caches leak significant information. Proposed detection mechanisms assume that all cache attacks cause more cache hits and cache misses than benign applications and use hardware performance counters for detection. In this article, we show that this assumption does not hold by developing a novel attack technique: the Flush+Flush attack. The Flush+Flush attack only relies on the execution time of the flush instruction, which depends on whether data is cached or not. Flush+Flush does not make any memory accesses, contrary to any other cache attack. Thus, it causes no cache misses at all and the number of cache hits is re...
ACM Computing Classification System: Hardware_MEMORYSTRUCTURES
free text keywords: Covert channel, Cache invalidation, Execution time, Cache attack, Cache, Computer security, computer.software_genre, computer, Computer science, Computer Science - Cryptography and Security
Related Organizations
Funded by
  • Funder: European Commission (EC)
  • Project Code: 644052
  • Funding stream: H2020 | RIA
Multi-entity-security using active Transmission Technology for improved Handling of Exportable security credentials Without privacy restrictions
  • Funder: European Commission (EC)
  • Project Code: 610436
  • Funding stream: FP7 | SP1 | ICT
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Other literature type . 2016
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publication . Conference object . Other literature type . Part of book or chapter of book . Preprint . 2016

Flush+Flush: A Fast and Stealthy Cache Attack

Daniel Gruss;