publication . Doctoral thesis . 2013

Low power predictable memory and processing architectures

Chen, Jiaoyan;
Open Access English
  • Published: 01 Jan 2013
  • Publisher: University College Cork
  • Country: Finland
Abstract
Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shor...
Subjects
free text keywords: Low power, Adiabatic, Asynchronous, Predictable, Electric power--Conservation, Electric leakage--Prevention, Metal oxide semiconductors, Complementary--Design and construction, Electronic digital computers--Power supply
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