Modeling a spacewire architecture using timed automata to compute worst-case end-to-end delays

Conference object English OPEN
Ermont, Jérôme ; Fraboul, Christian (2013)
  • Publisher: IEEE
  • Related identifiers: doi: 10.1109/ETFA.2013.6648072
  • Subject: [ INFO.INFO-NI ] Computer Science [cs]/Networking and Internet Architecture [cs.NI] | Systèmes embarqués | [ INFO.INFO-AR ] Computer Science [cs]/Hardware Architecture [cs.AR] | Worst-case delays analysis | Réseaux et télécommunications | Spacewire network | Timed automata | [ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems | UPPAAL modeling | [ INFO.INFO-OS ] Computer Science [cs]/Operating Systems [cs.OS] | Système d'exploitation | Architectures Matérielles

International audience; Spacewire is a real-time communication network for use onboard satellites. It has been designed to transmit both payload and control/command data. To guarantee that communications respect the real-time constraints, designers use tools to compute the worst-case end-to-end delays. Among these tools, recursive flow analysis and Network Calculus approaches have been studied. This paper proposes to use the model-checking approach based on timed automata. A case study based on an industrial one is shown. Our approach is compared with recursive flow analysis and Network Calculus.
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