Single Bit Radar Systems for Digital Integration

Doctoral thesis English OPEN
Bjørndal, Øystein;
(2017)

Small, low cost, radar systems have exciting applications in monitoring and imaging for the industrial, healthcare and Internet of Things (IoT) sectors. We here explore, and show the feasibility of, several single bit square wave radar architectures; that benefits from ... View more
  • References (12)
    12 references, page 1 of 2

    [2] R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. Balsara, “Time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” in Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE, June 2005.

    [3] J. Daniels, W. Dehaene, M. S. J. Steyaert, and A. Wiesbauer, “A/D conversion using asynchronous Delta-Sigma modulation and Time-toDigital conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, 2010.

    [4] P. A. Nuyts, P. Reynaert, and W. Dehaene, “Continuous-time digital design techniques,” in Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission. Springer, 2014, ch. 4.

    [5] Ø. Bjørndal, S.-E. Hamran, and T. S. Lande, “UWB waveform generator for digital CMOS radar,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015.

    [6] S.-J. Lee, K. Kim, H. Kim, N. Cho, and H.-J. Yoo, “Adaptive networkon-chip with wave-front train serialization scheme,” in VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on, June 2005.

    [7] B. C. Hien, S.-M. Kim, and K. Cho, “Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces,” in Quality Electronic Design (ASQED), 2012 4th Asia Symposium on, July 2012.

    [8] R. Dobkin, M. Moyal, A. Kolodny, and R. Ginosar, “Asynchronous current mode serial communication,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 7, July 2010.

    [9] A. Jaiswal, D. Walk, Y. Fang, and K. Hofmann, “Low-power high-speed on-chip asynchronous wave-pipelined CML SerDes,” in System-on-Chip Conference (SOCC), 2014 27th IEEE International, Sept 2014.

    [10] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital integrated circuits. Prentice hall Englewood Cliffs, 2002, vol. 2.

    [11] B. I. Abdulrazzaq, I. Abdul Halin, S. Kawahito, R. M. Sidek, S. Shafie, and N. A. M. Yunus, “A review on high-resolution CMOS delay lines: [GKSN11] A. Ghaffari, E. A. M. Klumperink, M. C. M. Soer, and B. Nauta. Tunable High-Q N-Path Band-Pass filters: Modeling and verification. IEEE Journal of Solid-State Circuits, 46(5):998-1010, 2011. doi:10.1109/JSSC.2011.2117010.

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