FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
BLOCK, Henry; MARUYAMA, Tsutomu;
- Publisher: 電子情報通信学会
- Journal: IEICE transactions on information and systems,volume E100.D,issue 2,pages256-264 (issn: 0916-8532)
- Publisher copyright policies & self-archiving
- Subject: 情報学
In this paper, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with a maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Progressive Neighborhood and the Indirect Calculatio... View more