publication . Article . 2017

Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5

Karim Shahbazi; Mohammad Eshghi; Reza Faghih Mirzaee;
Open Access
  • Published: 01 Aug 2017 Journal: Engineering Science and Technology, an International Journal, volume 20, pages 1,308-1,317 (issn: 2215-0986, Copyright policy)
  • Publisher: Elsevier BV
Abstract
Abstract In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific instructions for the above cryptographic algorithms. The proposed architecture has nine function units and two data buses. It has also two types of 32-bit instruction formats for executing Memory Reference (M.R.), Register Reference (R.R.), and Input/Output Reference (I/O R.) instructions. The maximum achieved frequency is 166.916 MHz. The encoded output results of the encryption process of a 128-bit input block are obtained after 122, 146 and 170 clock cycles for AES-128, AES-192, and AES-256, res...
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Subjects
ACM Computing Classification System: Hardware_ARITHMETICANDLOGICSTRUCTURES
free text keywords: ASIP, AES, Crypto Processor, IDEA, MD5, Throughput, Computer hardware, business.industry, business, Latency (engineering), Hash function, Instructions per cycle, Cryptography, Parallel computing, Encryption, Implementation, Computer science, lcsh:Engineering (General). Civil engineering (General), lcsh:TA1-2040
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