[7] IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009), IEEE Standard for SystemVerilog-Unified hardware design, specification, and verification language, [Online]. (2013).

[8] Y. Hung-Yi, Highly automated and efficient simulation environment with UVM, 2014 Int. Symp. VLSI Design, Autom. and Test (VLSI-DAT) (2013) 1.

[9] Y. Young-Nam, K. Jae-Beom, K. Nam-Do, M. Byeong, Beyond UVM for practical SoC verification, 2011 Int. SoC Design Conf. (ISOCC) (2011) 158.

[10] G. Zhong, J. Zhou, B. Xia, Parameter and UVM, making a layered testbench powerful, 2013 IEEE Int. Conf. ASIC (ASICON) (2013) 1.

[11] T. Poikela et al., Architectural modeling of pixel readout chips Velopix and Timepix3, 2012 JINST 7 C01093.

[12] V. Zivkovic et al., The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project, 2012 JINST 7 C02050.

[13] T. Binoth, C. Buttar, P.J. Clark, E.W.N. Glover, LHC Physics, Taylor & Francis, 2012.

[14] CERN, ROOT - A Data Analysis Framework, [Online]. (2014).

[15] D. Arutinov et al., Digital architecture and interface of the new ATLAS pixel front-end IC for upgraded LHC luminosity, IEEE Trans. Nucl. Sci. 56 (2009) 388.