publication . Article . Conference object . 2012

SEU tolerant memory design for the ATLAS pixel readout chip

Maurice Garcia-Sciveres; F. Gensolen; P. Breugnon; Y. Lu; Malte Backhaus; J.D. Schipper; R. Kluit; L. M. Caminada; D. Arutinov; A. Mekkaoui; ...
Open Access English
  • Published: 17 Sep 2012
  • Publisher: JINST
  • Country: France
Abstract
International audience; The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.
Subjects
ACM Computing Classification System: Hardware_PERFORMANCEANDRELIABILITYHardware_MEMORYSTRUCTURES
free text keywords: Detectors and Experimental Techniques, Microelectronics and interconnection technology [3], Shareable IP Blocks for HEP [3.3], Front-end electronics for detector readout, Analogue electronic circuits, Radiation-hard electronics, Radiation damage to electronic components, 29.40.Gx Tracking and position-sensitive detectors ; 85.30.Tv Field effect devices, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Instrumentation, Mathematical Physics, Dice, Upgrade, Computer hardware, business.industry, business, Chip, Atlas (anatomy), medicine.anatomical_structure, medicine, Pixel, Computer science, Electrical engineering, Cmos process
Funded by
EC| AIDA
Project
AIDA
Advanced European Infrastructures for Detectors at Accelerators
  • Funder: European Commission (EC)
  • Project Code: 262025
  • Funding stream: FP7 | SP4 | INFRA
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