De l’ingénierie de contacts métalliques aux transistors 3D à grille entourante : Architectures alternatives pour MOS nanométriques

Other literature type French OPEN
Larrieu, Guilhem;
(2016)
  • Publisher: HAL CCSD
  • Subject: nanofils | transistor MOS | Transistor MOS scaling | nano- engineering | Miniaturisation | contacts métalliques | metallic contacts | nanostructuration | [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics | ségrégation de dopants | nanowires | dopant segregation | assemblage nanostructures | large scale assembly of nanostructures

Pas de resumes; Lors des 40 dernières années, la technologie CMOS a permis une véritable révolution dans le traitement de l’information, sans cesse amélioré grâce à la diminution continue des dimensions des composants. L’évolution récente a conduit à la réduction des di... View more
  • References (45)
    45 references, page 1 of 5

    combination of capillary and dielectrophoresis-driven assembly methods for wafer scale integration of carbon nanotubes-based nanocarpets”, Nanotechnology, 23, 9 (2012) 095303 R10. X.L. Han, G. Larrieu, E. Dubois, F. Cristiano, “Carrier injection at silicide/silicon interfaces in nanowire based-nanocontacts”, Surf. Sci., 606, 9-10 (2012) 836-839.

    R11. N. Reckinger, X.H. Tang, E. Dubois, G. Larrieu, D. Flandre, J.P. Raskin, A. Afzalian, "Low temperature tunneling current enhancement in silicide/Si Schottky contacts with nanoscale barrier width" , Appl. Phys. Lett. 98, 11 (2011) 112102−1−3.

    R12. X.L. Han, G. Larrieu, P.F. Fazzini, E. Dubois “Realization of ultra-dense arrays of vertical silicon NWs with defect free surface and perfect anisotropy using a top-down approach” Microelectron.

    Eng., 88, 8 (2011) 2622-2624.

    R13. G. Larrieu, E. Dubois, “CMOS inverter based on Schottky source-drain MOS technology with low temperature dopant segregation”, IEEE Electron Device Lett., 32, 6 (2011) 728-730.

    R14. S. Plissard, G. Larrieu, X. Wallart, P. Caroff “High yield of self-catalyzed GaAs nanowire arrays grown on silicon via gallium droplet positioning”, Nanotechnology, 22 (2011) 275602.

    R15. A Laszcz, J. Ratajczak, A. Czerwinski, J Katcki, N Breil, G Larrieu, E Dubois, "TEM studies of PtSi low Schottky−barrier contacts for source/drain in MOS transistors " Cent. Eur. Journ. of Phys., 9, 2 (2011) 423−427.

    R16. G. Larrieu, E. Dubois, D. Ducatteau, “CMOS integration using low thermal budget dopantsegregated metallic S/D junctions on thin-body SOI”, ECS Trans., 41, 7 (2011) 275-282.

    R17. X.L. Han, G. Larrieu, E. Dubois, “Realization of vertical silicon nanowire networks with an ultrahigh density by top-down approach”, Journal of Nanoscience and Nanotechnology, 10, (2010),7423- 7427.

    R18. S. Plissard , K.A Dick, G. Larrieu, S. Godey, A. Addad, X. Wallart, P. Caroff “Gold-free growth of GaAs nanowires on silicon: arrays and polytypism”, Nanotechnology, 21 (2010) 385602.

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