High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code,... View more
 Wipliez, M, “Compilation Infrastructure for Dataflow Programs,” Ph.D. dissertation, National Institute of Applied Sciences (INSA) - Rennes, 2010.
 N. Siret, M. Wipliez, J. Nezan, and A. Rhatay, “Hardware code generation from dataflow programs,” in IEEE International conference on Design and Architectures for Signal and Image Processing (DASIP), 2010, pp. 113 -120.
 G. Martin and G. Smith, “High-level synthesis: Past, present, and future,” IEEE Design & Test of Computers, pp. 18-25, 2009.
 P. Coussy and A. Morawiec, High-level synthesis: from algorithm to digital circuit. Springer Verlag, 2008.
 I. Berkeley Design Technology, “An independent evaluation of: Highlevel synthesis tools for xilinx fpgas,” www.BDTI.com, Tech. Rep., 2010.
 IEEE Std 1666 - IEEE Standard SystemC Language Reference Manual, IEEE Std 1666-2005, 2005.
 J. Castillo, P. Huerta, and J. Mart´ınez, “An Open-Source Tool for SystemC to Verilog Automatic Translation,” in Latin American Applied Research, 2007.
 P. Coussy, D. Gajski, M. Meredith, and A. Takach, “An Introduction to High-Level Synthesis,” Design Test of Computers, IEEE, vol. 26, no. 4, pp. 8 -17, 2009.
 M. Mattavelli, I. Amer, and M. Raulet, “The Reconfigurable Video Coding Standard [Standards in a Nutshell],” IEEE Signal Processing Magazine, vol. 27, no. 3, pp. 159-167, may 2010.
 M. Wipliez, G. Roquier, and J.-F. Nezan, “Software Code Generation for the RVC-CAL Language,” Springer journal of Signal Processing Systems, 2009.