Generation of Efficient High-Level Hardware Code from Dataflow Programs

Conference object English OPEN
Siret , Nicolas ; Wipliez , Matthieu ; Nezan , Jean François ; Palumbo , Francesca (2012)
  • Publisher: HAL CCSD
  • Subject: dataflow models | [ INFO.INFO-MM ] Computer Science [cs]/Multimedia [cs.MM] | high level synthesis | [ SPI.TRON ] Engineering Sciences [physics]/Electronics | [ INFO.INFO-SE ] Computer Science [cs]/Software Engineering [cs.SE] | [ INFO.INFO-PL ] Computer Science [cs]/Programming Languages [cs.PL]

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code,... View more
  • References (17)
    17 references, page 1 of 2

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    [7] J. Castillo, P. Huerta, and J. Mart´ınez, “An Open-Source Tool for SystemC to Verilog Automatic Translation,” in Latin American Applied Research, 2007.

    [8] P. Coussy, D. Gajski, M. Meredith, and A. Takach, “An Introduction to High-Level Synthesis,” Design Test of Computers, IEEE, vol. 26, no. 4, pp. 8 -17, 2009.

    [9] M. Mattavelli, I. Amer, and M. Raulet, “The Reconfigurable Video Coding Standard [Standards in a Nutshell],” IEEE Signal Processing Magazine, vol. 27, no. 3, pp. 159-167, may 2010.

    [10] M. Wipliez, G. Roquier, and J.-F. Nezan, “Software Code Generation for the RVC-CAL Language,” Springer journal of Signal Processing Systems, 2009.

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