publication . Article . 2013

A 10MS/s 8-bit charge-redistribution ADC for hybrid pixel applications in 65m CMOS

Hans Krüger; L. Germic; Tomasz Hemperek; M. Koch; Norbert Wermes; Tetsuichi Kishishita;
Open Access
  • Published: 01 Jan 2013 Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, volume 732, pages 506-510 (issn: 0168-9002, Copyright policy)
  • Publisher: Elsevier BV
Abstract
Abstract The design and measurement results of an 8-bit SAR ADC, based on a charge-redistribution DAC, are presented. This ADC is characterized by superior power efficiency and small area, realized by employing a lateral metal–metal capacitor array and a dynamic two-stage comparator. To avoid the need for a high-speed clock and its associated power consumption, an asynchronous logic was implemented in a logic control cell. A test chip has been developed in a 65 nm CMOS technology, including eight ADC channels with different layout flavors of the capacitor array, a transimpedance amplifier as a signal input structure, a serializer, and a custom-made LVDS driver f...
Subjects
ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_PERFORMANCEANDRELIABILITY
free text keywords: Nuclear and High Energy Physics, Instrumentation, Detectors and Experimental Techniques, Microelectronics and interconnection technology [3], Shareable IP Blocks for HEP [3.3], Comparator, Electrical efficiency, Physics, Transimpedance amplifier, Amplifier, CMOS, Asynchronous circuit, Successive approximation ADC, Analog-to-digital converter, law.invention, law, Electrical engineering, business.industry, business
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